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Welcome to the born-again comp-arch.net wiki! ... Save the applause until fully resuscitated.

About the Comp-Arch wiki

In these early days of the resuscitation, the pages will be collected essentially randomly. Eventually I will restore the original hierarchy of pages, and hopefully improve it by automation (which should be easier nowadays since I am using the git wiki with text files rather than MediaWiki).

Random Initial Pages

• date written or updated

Technical

Tiling for TLBs and Caches

Capabilities with and without Special Tagged Memory - 2020-11-16

Atomics vs Load Linked & Store Conditional (LL & SC)

• multiword atomics
• multiword LL & SC

Conditional Select, Move, Merge branchless instructions

Debugging

There will always be a need for one more privilege level

Large pages via Contiguous PTEs and partial occupancy

Thoughts for Portable ISAs

Endianness related Topics

• Convert to Specified Endianness
• Byte Address Invariant Endianness versus Word Data Value Invariant Endianness
• Endianness means that Packed Vector ISAs must specify Element Width

Vector ISA topics

• SIMD packed vectors
• fixed #bits vs fixed #elements vector ISAs

Negative Offsets, Indexes, and Counters

Breaking out of the RISC 3-register, 2-input 1-output straitjacket

• load instructions that write more than one register

Instruction Encoding Notation

Permutations, Shuffles, Packs, etc.

Possibly useful references and collections of links

• Mark-Himelstein's-RISC-V-information-links-spreadsheet