Endianness means that Packed Vector ISAs must specify Element Width

A SIMD packed vector ISA where memory access is always load a fixed number of bits does not need to specify element width on a machine that only supports a single endianness.

however, if the processor has endianness modes, e.g. big/little, the vector loader and store instructions need to specify the endianness, so that the data elements can be byte swapping, while the vector elements are loaded in a consistent order, typically with element zero corresponding to bit zero of the packed data register.

See fixed #bits vs fixed #elements vector instructions