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ARM support #955

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wants to merge 308 commits into from
Closed

ARM support #955

wants to merge 308 commits into from

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regehr
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@regehr regehr commented Nov 2, 2023

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regehr and others added 30 commits January 10, 2023 16:52
add support for ADC instruction
…de is still there but it can start to be removed now
regehr and others added 27 commits September 25, 2023 09:54
…i, STRDui and ADDv8i8 (#8)

* Created Entries for NEON registers V0-V31
Allocated memory in Backing register store for V0-V31
Created dealiasing rules from H, S, D floating-point registers to V registers
Removed some redundant code lines in existing code

* Created a function to map ARM registers to the Backing Store
Added SIMD/FP registers to getRegSize and mapRegToBackingReg
Added support for :lo12: relocation specifier in readFromOperand
Modified writeToOutputReg to check Destination Register instead of Instruction Size for value extending rules
Supported writing to a 128 bit register in writeToOutputReg by ZExtding any smaller value

* Added a test for vector add ADDv8i8 and a test for scalar ADD
Commented code blocking vector instructions
Added ADDv8i8, LDRDui and STRDui as 64 bit instructions

* Update adjust_src.cpp

* Update adjust_src.cpp

* Changed Vn to Qn regs
Renamed GOT to instExprVarMap
Wrote mapExprVar and getExprVar functions and replaced existing code blocks with these function calls
Generalized relocation specifier identification

* Revert "Update adjust_src.cpp"

This reverts commit 4fd9c3e.
* Corrected code mapping ADRP instructions to expressions
Added Expr cases to LDRHHui, LDRBBui, LDRWui and LDRDui

* Fixed getRegSize by added leftout registers WZR, XZR, WSP, SP, LR and FP
Added more comments
Handled 128 bit regs for readFromReg
Removed vector register from get ParamsLoadImmed and getParamsStoreImmed as only general purpose regs are used for memory
Added LDRBui

* Fixed bug where a load was created and stored in "a" without it being used for some PC-relative addressing instructions like ADDXri.
Fixed getExprVar by breaking loop through visited ADRP instrucitons
Added more comments

* Adding LDRHui, STRHui, and ADDv4i16

* Generalizing Vector Add instruction code
Added function to compute bit width (getBitWidth) of some Value (scalar or vector) and replaced getIntegerBitWidth function calls with this new function

* Moved unhandled tests to "unhandled" folder
@nunoplopes nunoplopes changed the title New adjust src ARM support Nov 17, 2023
@regehr regehr closed this Nov 25, 2023
@regehr regehr deleted the new-adjust-src branch November 25, 2023 19:55
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4 participants