ASL optimizer: An optimizer performing TILOS-like algorithm for exploring energy/delay trade-offs in ASL circuits

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Author: Zhaoxin Liang @ University of Minnesota - Twin Cities, VLSI - EDA group.

Description: This repository contains C++ souce codes for the ASL geometric optimizer.

Version: 1.0 (Previous to Oct. 01, 2017)

License: by Zhaoxin Liang

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03/29/2023

Revisiting the repo.

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Note 16 (Feb. 11, 2018):

1. Makefile updated and source/header reorganized.

Note 15 (Oct. 1, 2017):

1. Reformatted the README.md and added ISCAS benchmarks to the repository.

2. Created a bash version execution script as iscas_benchmarks.sh.

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Old change logs

Change logs previous to Oct. 01, 2017, as history reference only

Note 1: Created for ICCAD 2015 submission.

Note 2: Version 1.0 uses Eigen: http://eigen.tuxfamily.org/index.php?title=Main_Page for matrix computation in MNA.cpp.

Note 3: Sync tested.

Note 4: v6 does not include incremental timing analysis, it is included in v5.

Note 5: v7 removed the STA performance in every TILOS iterations.

Note 6: v8 added incremental timing analysis back.

Note 7: The "same delay reduction flag" is removed in v9, yet the STA is recovered for the evaluation after each adaption.

Note 8: In version 10, a bug in incremental timing analysis by adding the "gate_ptr->opt_ptrs[i]->RTready != 0" in "ReachTimeReadyReset" function.

Note 9: In version 11, removed the recalculation and use recovery from stored value to save runtime in each iteration.

Note 10: In version 12, the adaption should also reuse previous calculation results. (it seems that the double precision matching issue with map<pair<double, double>, double> Delay3to1Table, meaning the value you calculated for double in precalculation and later matching function cannot match well. trying to use pair<int, int> instead)

Note 11: In version 13, recalculation of delays related to the sized gates is adjusted, so some unnecessary recalculations are removed, for example, if the output magnet is sized, only the internal delay and its fan-out interconnect delay should be recalculated, no need to recaclulate the input interconnect delays of this gate. (Finished. the most time-consuming part is the calculation of the gate/interconnect delays, so precalculation/reuse/avoiding unnecessary calculation are good ways to reduce runtime.)

Note 12 (Aug. 11, 2015): This program is used to generate data in JxCDC manuscript in Aug. 8, 2015. Three sets of technology parameters were used with the [double SpacingDis (from mylib.cpp)] parameter set to the same value as the corresponding spin diffusion lengths in the gate.h. For fast simulation speed, calculation and output of Power and Area is disabled by commenting function [vector PowerArea = PowerAreaCalc(gate_vec0);] in row 653 of mylib.cpp and turn off the output line a few rows later [outfile<<CURRENT_ITERATION+1<<" "<<MaxDelay0<<" "<<PowerArea[0]<<" "<<PowerArea[1]<<endl;].

Note 13 (Oct. 16, 2015): New models considering the contacts and grounds were added to the delay calculation part.o.

Note 14: copying a clone to local.