ARM Cortex-M series CPU models with optional features default to having those features enabled

[castholm]

For example, the ARM Cortex-M7 has three options for FPU:

• no FPU
• single-precision FPU
• single- and double-precision FPU

Specifying thumb-freestanding-eabihf as the target and cortex_m7 as the CPU results in all optional SP+DP floating point features being enabled.

For example: currently, if a user wants to compile for the Playdate console, which uses a Cortex-M7 with a single-precision FPU, it requires the user to dig through the source file for std.Target.arm to figure out which double-precision features they need to disable. This is not trivial since it requires looking up the definition of fp_armv8d16 to see that it adds vfp4d16, vfp4d16 to see that it adds vfp3d16 and so on recursively until all offending features have been identified.
In the end you end with the CPU string cortex_m7-fp_armv8d16-vfp4d16-vfp3d16-vfp2-fp64-fpregs64.

This problem with Cortex-M7 in praticular was actually mentioned in passing in an issue in 2020 (#4631 (comment), #4631 (comment)), where Andrew wrote

If the FPU is not determinable only by specifying the cpu model as cortex-m7, then the user should have to specify the FPU. The features attached to a given CPU model should be only what is guaranteed to be available in the hardware, and optional features are supposed to be supplied separately.

If I'm interpreting this right and it still holds today, this means that CPU models with optional features should default to having them disabled.
So specifying just cortex_m7 should mean that no FPU features are enabled and in order to build for a SP or SP+DP Cortex-M7 you need to use cortex_m7+fp_armv8d16sp or cortex_m7+fp_armv8d16 respectively.

From quickly skimming through std.Target.arm, the are other affected models like M4, M33 and M35P.

ARM provides a helpful comparison table that lists optional features in PDF form on their website. The Wikipedia page for ARM Cortex-M also lists a (less authoritative) overview of optional features (scroll down to the "ARM Cortex-M instruction variations" table).

There are probably other CPU models with optional features that have similar issues.