MIPS-pipeline-CPU

MIPS pipeline CPU for experiment of computer organization and design

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
EXE_MEM.v		EXE_MEM.v
ID_EXE.v		ID_EXE.v
IF_ID.v		IF_ID.v
MEM_WB.v		MEM_WB.v
README.md		README.md
code3.txt		code3.txt
ctrl_encode_def.v		ctrl_encode_def.v
instruction_def.v		instruction_def.v
j_ctrl.v		j_ctrl.v
mips_tb.v		mips_tb.v
pipe_DMem.v		pipe_DMem.v
pipe_IM.v		pipe_IM.v
pipe_PcUnit.v		pipe_PcUnit.v
pipe_adder.v		pipe_adder.v
pipe_alu.v		pipe_alu.v
pipe_ctrl.v		pipe_ctrl.v
pipe_extender.v		pipe_extender.v
pipe_forward_a.v		pipe_forward_a.v
pipe_forward_b.v		pipe_forward_b.v
pipe_forward_ctrl.v		pipe_forward_ctrl.v
pipe_forward_m.v		pipe_forward_m.v
pipe_gpr.v		pipe_gpr.v
pipe_hazard_detect.v		pipe_hazard_detect.v
pipe_mips.v		pipe_mips.v
pipe_rtmux.v		pipe_rtmux.v
pipe_wbmux.v		pipe_wbmux.v
pipe_wbrmux.v		pipe_wbrmux.v
wbrmux.v		wbrmux.v

Provide feedback