[LLVM][XTHeadVector] Implement intrinsics for vwmul/vwmulu/vwmulsu. (l…

…lvm#65)

* [LLVM][XTHeadVector] Define intrinsic functions for vwmul/vwmulu/vwmulsu.

* [LLVM][XTHeadVector] Define pseudos and pats.

* [LLVM][XTHeadVector] Add tests.

* [NFC][XTHeadVector] Update README.

README.md

@@ -47,6 +47,7 @@ Any feature not listed below but present in the specification should be consider
     - (Done) `12.7 Vector Integer Comparison Instructions`
     - (Done) `12.8. Vector Integer Min/Max Instructions`
     - (Done) `12.10. Vector Integer Divide Instructions`
+    - (Done) `12.11. Vector Widening Integer Multiply Instructions`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -693,6 +693,11 @@ let TargetPrefix = "riscv" in {
   defm th_vdiv : XVBinaryAAX;
   defm th_vremu : XVBinaryAAX;
   defm th_vrem : XVBinaryAAX;
+
+  // 12.11. Vector Widening Integer Multiply Instructions
+  defm th_vwmul : XVBinaryABX;
+  defm th_vwmulu : XVBinaryABX;
+  defm th_vwmulsu : XVBinaryABX;
 } // TargetPrefix = "riscv"
 
 let TargetPrefix = "riscv" in {

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -1946,6 +1946,21 @@ multiclass XVPseudoVDIV_VV_VX {
   }
 }
 
+multiclass XVPseudoVWMUL_VV_VX {
+  foreach m = MxListWXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVIWMulV_MX = !cast<SchedWrite>("WriteVIWMulV_" # mx);
+    defvar WriteVIWMulX_MX = !cast<SchedWrite>("WriteVIWMulX_" # mx);
+    defvar ReadVIWMulV_MX = !cast<SchedRead>("ReadVIWMulV_" # mx);
+    defvar ReadVIWMulX_MX = !cast<SchedRead>("ReadVIWMulX_" # mx);
+
+    defm "" : XVPseudoBinaryW_VV<m>,
+              Sched<[WriteVIWMulV_MX, ReadVIWMulV_MX, ReadVIWMulV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryW_VX<m>,
+              Sched<[WriteVIWMulX_MX, ReadVIWMulV_MX, ReadVIWMulX_MX, ReadVMask]>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns for the XTHeadVector extension.
 //===----------------------------------------------------------------------===//
@@ -2644,6 +2659,21 @@ let Predicates = [HasVendorXTHeadV] in {
   defm : XVPatBinaryV_VV_VX<"int_riscv_th_vrem", "PseudoTH_VREM", AllIntegerXVectors, isSEWAware=1>;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 12.11. Vector Widening Integer Multiply Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV] in {
+  defm PseudoTH_VWMUL   : XVPseudoVWMUL_VV_VX;
+  defm PseudoTH_VWMULU  : XVPseudoVWMUL_VV_VX;
+  defm PseudoTH_VWMULSU : XVPseudoVWMUL_VV_VX;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwmul", "PseudoTH_VWMUL", AllWidenableIntXVectors>;
+  defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwmulu", "PseudoTH_VWMULU", AllWidenableIntXVectors>;
+  defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwmulsu", "PseudoTH_VWMULSU", AllWidenableIntXVectors>;
+} // Predicates = [HasVendorXTHeadV]
+
 //===----------------------------------------------------------------------===//
 // 12.14. Vector Integer Merge and Move Instructions
 //===----------------------------------------------------------------------===//