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Decouple timers from system clock #16958

Merged
merged 33 commits into from
Jul 24, 2019
Merged

Decouple timers from system clock #16958

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c175847
drivers: i2c_bitbang: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
pizi-nordic Apr 23, 2019
060b4cb
drivers: pwm_qmsi: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
pizi-nordic Apr 23, 2019
ab48cfc
drivers: timer: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
pizi-nordic Apr 23, 2019
4484bd1
debug: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
pizi-nordic Apr 23, 2019
ffa9369
logging: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
pizi-nordic Apr 23, 2019
4bbc37b
tests: benchmarks: Do not use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
pizi-nordic Apr 23, 2019
94f0762
drivers: i2c_cc32xx: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
55a832a
soc: snps_arc_iot: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
d6d0037
soc: sam3x: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
3a72781
soc: sam4s: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
caa08fb
soc: samd2x: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
c81013e
soc: samr21: Get CPU clock frequency from DTS
pizi-nordic May 29, 2019
02a7d41
soc: same70: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
e953624
soc: k6x: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
d7e3316
soc: kl2x: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
28a2444
soc: kwx: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
c28c44b
soc: lpc54xxx: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
59812b0
arch: xtensa: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
788e4e8
soc: msp432p4xx: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
bb7b545
soc: nxp_rt: Get system clock frequency from DTS
pizi-nordic May 29, 2019
c8c9cf3
drivers: beetle_clock_control: Get CPU clock frequency from DTS
pizi-nordic Apr 11, 2019
75d1fc7
logging: log_backend_swo: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
2b2800d
drivers: spi_dw: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
9000a51
drivers: uart_cmsdk_apb: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
0e25db3
drivers: uart_pl011: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
3098758
drivers: uart_cc32xx: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
8219a3a
drivers: uart_msp432p4xx: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
7ae312a
drivers: uart_qmsi: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
1ef851b
drivers: uart_stellaris: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
d5db8cf
drivers: uart_cc13xx_cc26xx: Get clock frequency from DTS
pizi-nordic May 29, 2019
bccdf56
drivers: wdog_cmsdk_apb: Get clock frequency from DTS
pizi-nordic Apr 11, 2019
efebd07
drivers: adc_stm32: Get clock frequency from DTS
pizi-nordic May 30, 2019
7850fb5
debug: tracing: Fix compilation error
pizi-nordic Jun 19, 2019
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6 changes: 2 additions & 4 deletions arch/xtensa/include/xtensa_rtos.h
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Original file line number Diff line number Diff line change
Expand Up @@ -46,10 +46,8 @@
#define XT_BOARD 1
#endif

#ifdef CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#undef XT_CLOCK_FREQ
#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#endif
#undef XT_CLOCK_FREQ
#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY

#ifndef XT_TIMER_INDEX
#if defined configXT_TIMER_INDEX
Expand Down
2 changes: 1 addition & 1 deletion arch/xtensa/include/xtensa_timer.h
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Expand Up @@ -115,7 +115,7 @@
* anyway!).
*/
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#endif

#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
Expand Down
2 changes: 1 addition & 1 deletion drivers/adc/adc_stm32.c
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Expand Up @@ -557,7 +557,7 @@ static int adc_stm32_init(struct device *dev)
LOG_ERR("ADC clock rate get error.");
}

wait_cycles = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / adc_rate *
wait_cycles = SystemCoreClock / adc_rate *
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Why is this SystemCoreClock vs sys_clock_hw_cycles_per_sec()?

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Requested by code owner for this file some review rounds ago. Note, that there should be CPU frequency as the wait_cycles is used to spin around:

	for (int i = wait_cycles; i >= 0; i--) {
	}

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@erwango does this need to be SystemCoreClock?

LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES;

for (int i = wait_cycles; i >= 0; i--) {
Expand Down
2 changes: 1 addition & 1 deletion drivers/clock_control/beetle_clock_control.c
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Expand Up @@ -233,7 +233,7 @@ static int beetle_clock_control_init(struct device *dev)

static const struct beetle_clock_control_cfg_t beetle_cc_cfg = {
.clock_control_id = 0,
.freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.freq = DT_ARM_CORTEX_M3_0_CLOCK_FREQUENCY,
};

/**
Expand Down
18 changes: 5 additions & 13 deletions drivers/i2c/i2c_bitbang.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,17 +37,7 @@
#define T_BUF T_LOW

#define NS_TO_SYS_CLOCK_HW_CYCLES(ns) \
((u64_t)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC * (ns) / NSEC_PER_SEC + 1)

static const u32_t delays_fast[] = {
[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300),
[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(600),
};

static const u32_t delays_standard[] = {
[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700),
[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000),
};
((u64_t)sys_clock_hw_cycles_per_sec() * (ns) / NSEC_PER_SEC + 1)

int i2c_bitbang_configure(struct i2c_bitbang *context, u32_t dev_config)
{
Expand All @@ -59,10 +49,12 @@ int i2c_bitbang_configure(struct i2c_bitbang *context, u32_t dev_config)
/* Setup speed to use */
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
context->delays = delays_standard;
context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700);
context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000);
break;
case I2C_SPEED_FAST:
context->delays = delays_fast;
context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300);
context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(600);
break;
default:
return -ENOTSUP;
Expand Down
2 changes: 1 addition & 1 deletion drivers/i2c/i2c_bitbang.h
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ struct i2c_bitbang_io {
struct i2c_bitbang {
const struct i2c_bitbang_io *io;
void *io_context;
const u32_t *delays;
u32_t delays[2];
};

/**
Expand Down
2 changes: 1 addition & 1 deletion drivers/i2c/i2c_cc32xx.c
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Expand Up @@ -103,7 +103,7 @@ static int i2c_cc32xx_configure(struct device *dev, u32_t dev_config_raw)
return -EINVAL;
}

MAP_I2CMasterInitExpClk(base, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
MAP_I2CMasterInitExpClk(base, DT_I2C_0_CLOCK_FREQUENCY,
bitrate_id);

return 0;
Expand Down
2 changes: 1 addition & 1 deletion drivers/pwm/pwm_qmsi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
#include "qm_pwm.h"
#include "clk.h"

#define HW_CLOCK_CYCLES_PER_USEC (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / \
#define HW_CLOCK_CYCLES_PER_USEC (sys_clock_hw_cycles_per_sec() / \
USEC_PER_SEC)

/* pwm uses 32 bits counter to control low and high period */
Expand Down
4 changes: 2 additions & 2 deletions drivers/serial/uart_cc13xx_cc26xx.c
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Expand Up @@ -361,7 +361,7 @@ static int uart_cc13xx_cc26xx_init_0(struct device *dev)

static const struct uart_device_config uart_cc13xx_cc26xx_config_0 = {
.regs = DT_TI_CC13XX_CC26XX_UART_40001000_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_TI_CC13XX_CC26XX_UART_40001000_CLOCKS_CLOCK_FREQUENCY,
};

static struct uart_cc13xx_cc26xx_data uart_cc13xx_cc26xx_data_0 = {
Expand Down Expand Up @@ -438,7 +438,7 @@ static int uart_cc13xx_cc26xx_init_1(struct device *dev)

static const struct uart_device_config uart_cc13xx_cc26xx_config_1 = {
.regs = DT_TI_CC13XX_CC26XX_UART_4000B000_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_TI_CC13XX_CC26XX_UART_4000B000_CLOCKS_CLOCK_FREQUENCY,
};

static struct uart_cc13xx_cc26xx_data uart_cc13xx_cc26xx_data_1 = {
Expand Down
2 changes: 1 addition & 1 deletion drivers/serial/uart_cc32xx.c
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Expand Up @@ -38,7 +38,7 @@ static void uart_cc32xx_isr(void *arg);

static const struct uart_device_config uart_cc32xx_dev_cfg_0 = {
.base = (void *)DT_TI_CC32XX_UART_4000C000_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_TI_CC32XX_UART_4000C000_CLOCKS_CLOCK_FREQUENCY,
};

static struct uart_cc32xx_dev_data_t uart_cc32xx_dev_data_0 = {
Expand Down
10 changes: 5 additions & 5 deletions drivers/serial/uart_cmsdk_apb.c
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Expand Up @@ -464,7 +464,7 @@ static void uart_cmsdk_apb_irq_config_func_0(struct device *dev);

static const struct uart_device_config uart_cmsdk_apb_dev_cfg_0 = {
.base = (u8_t *)DT_INST_0_ARM_CMSDK_UART_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_INST_0_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = uart_cmsdk_apb_irq_config_func_0,
#endif
Expand Down Expand Up @@ -529,7 +529,7 @@ static void uart_cmsdk_apb_irq_config_func_1(struct device *dev);

static const struct uart_device_config uart_cmsdk_apb_dev_cfg_1 = {
.base = (u8_t *)DT_INST_1_ARM_CMSDK_UART_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_INST_1_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = uart_cmsdk_apb_irq_config_func_1,
#endif
Expand Down Expand Up @@ -594,7 +594,7 @@ static void uart_cmsdk_apb_irq_config_func_2(struct device *dev);

static const struct uart_device_config uart_cmsdk_apb_dev_cfg_2 = {
.base = (u8_t *)DT_INST_2_ARM_CMSDK_UART_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_INST_2_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = uart_cmsdk_apb_irq_config_func_2,
#endif
Expand Down Expand Up @@ -659,7 +659,7 @@ static void uart_cmsdk_apb_irq_config_func_3(struct device *dev);

static const struct uart_device_config uart_cmsdk_apb_dev_cfg_3 = {
.base = (u8_t *)DT_INST_3_ARM_CMSDK_UART_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_INST_3_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = uart_cmsdk_apb_irq_config_func_3,
#endif
Expand Down Expand Up @@ -724,7 +724,7 @@ static void uart_cmsdk_apb_irq_config_func_4(struct device *dev);

static const struct uart_device_config uart_cmsdk_apb_dev_cfg_4 = {
.base = (u8_t *)DT_INST_4_ARM_CMSDK_UART_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_INST_4_ARM_CMSDK_UART_CLOCKS_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = uart_cmsdk_apb_irq_config_func_4,
#endif
Expand Down
2 changes: 1 addition & 1 deletion drivers/serial/uart_msp432p4xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ static void uart_msp432p4xx_isr(void *arg);

static const struct uart_device_config uart_msp432p4xx_dev_cfg_0 = {
.base = (void *)DT_UART_MSP432P4XX_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_UART_MSP432P4XX_CLOCK_FREQUENCY,
};

static struct uart_msp432p4xx_dev_data_t uart_msp432p4xx_dev_data_0 = {
Expand Down
8 changes: 4 additions & 4 deletions drivers/serial/uart_pl011.c
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Original file line number Diff line number Diff line change
Expand Up @@ -361,8 +361,8 @@ static int pl011_init(struct device *dev)
pl011_disable_fifo(dev);

/* Set baud rate */
ret = pl011_set_baudrate(dev, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
DEV_DATA(dev)->baud_rate);
ret = pl011_set_baudrate(dev, DEV_CFG(dev)->sys_clk_freq,
DEV_DATA(dev)->baud_rate);
if (ret != 0) {
return ret;
}
Expand Down Expand Up @@ -414,7 +414,7 @@ static void pl011_irq_config_func_0(struct device *dev);

static struct uart_device_config pl011_cfg_port_0 = {
.base = (u8_t *)DT_PL011_PORT0_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_PL011_PORT0_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = pl011_irq_config_func_0,
#endif
Expand Down Expand Up @@ -468,7 +468,7 @@ static void pl011_irq_config_func_1(struct device *dev);

static struct uart_device_config pl011_cfg_port_1 = {
.base = (u8_t *)DT_PL011_PORT1_BASE_ADDRESS,
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
.sys_clk_freq = DT_PL011_PORT1_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = pl011_irq_config_func_1,
#endif
Expand Down
30 changes: 20 additions & 10 deletions drivers/serial/uart_qmsi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,10 +20,10 @@

#define IIR_IID_NO_INTERRUPT_PENDING 0x01

#define DIVISOR_LOW(baudrate) \
((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / (16 * baudrate)) & 0xFF)
#define DIVISOR_HIGH(baudrate) \
(((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / (16 * baudrate)) & 0xFF00) >> 8)
#define DIVISOR_LOW(clock, baudrate) \
((clock / (16 * baudrate)) & 0xFF)
#define DIVISOR_HIGH(clock, baudrate) \
(((clock / (16 * baudrate)) & 0xFF00) >> 8)

/* Convenient macro to get the controller instance. */
#define GET_CONTROLLER_INSTANCE(dev) \
Expand All @@ -33,6 +33,7 @@
struct uart_qmsi_config_info {
qm_uart_t instance;
clk_periph_t clock_gate;
u32_t clock_frequency;
u32_t baud_divisor;
bool hw_fc;

Expand Down Expand Up @@ -140,9 +141,12 @@ static void irq_config_func_0(struct device *dev);
static const struct uart_qmsi_config_info config_info_0 = {
.instance = QM_UART_0,
.clock_gate = CLK_PERIPH_UARTA_REGISTER | CLK_PERIPH_CLK,
.clock_frequency = DT_UART_QMSI_0_CLOCK_FREQUENCY,
.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(
DIVISOR_HIGH(DT_UART_QMSI_0_BAUDRATE),
DIVISOR_LOW(DT_UART_QMSI_0_BAUDRATE),
DIVISOR_HIGH(DT_UART_QMSI_0_CLOCK_FREQUENCY,
DT_UART_QMSI_0_BAUDRATE),
DIVISOR_LOW(DT_UART_QMSI_0_CLOCK_FREQUENCY,
DT_UART_QMSI_0_BAUDRATE),
0),
#ifdef CONFIG_UART_QMSI_0_HW_FC
.hw_fc = true,
Expand All @@ -168,9 +172,12 @@ static void irq_config_func_1(struct device *dev);
static const struct uart_qmsi_config_info config_info_1 = {
.instance = QM_UART_1,
.clock_gate = CLK_PERIPH_UARTB_REGISTER | CLK_PERIPH_CLK,
.clock_frequency = DT_UART_QMSI_1_CLOCK_FREQUENCY,
.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(
DIVISOR_HIGH(DT_UART_QMSI_1_BAUDRATE),
DIVISOR_LOW(DT_UART_QMSI_1_BAUDRATE),
DIVISOR_HIGH(DT_UART_QMSI_1_CLOCK_FREQUENCY,
DT_UART_QMSI_1_BAUDRATE),
DIVISOR_LOW(DT_UART_QMSI_1_CLOCK_FREQUENCY,
DT_UART_QMSI_1_BAUDRATE),
0),
#ifdef CONFIG_UART_QMSI_1_HW_FC
.hw_fc = true,
Expand Down Expand Up @@ -405,13 +412,16 @@ static void irq_config_func_1(struct device *dev)
static int uart_qmsi_line_ctrl_set(struct device *dev, u32_t ctrl, u32_t val)
{
qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
const struct uart_qmsi_config_info *config = dev->config->config_info;
qm_uart_config_t cfg;

switch (ctrl) {
case LINE_CTRL_BAUD_RATE:
cfg.line_control = QM_UART[instance]->lcr;
cfg.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(DIVISOR_HIGH(val),
DIVISOR_LOW(val), 0);
cfg.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(
DIVISOR_HIGH(config->clock_frequency, val),
DIVISOR_LOW(config->clock_frequency, val),
0);
if (cfg.baud_divisor == 0) {
return -EINVAL;
}
Expand Down
6 changes: 3 additions & 3 deletions drivers/serial/uart_stellaris.c
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Original file line number Diff line number Diff line change
Expand Up @@ -634,7 +634,7 @@ static void irq_config_func_0(struct device *port);

static const struct uart_device_config uart_stellaris_dev_cfg_0 = {
.base = (u8_t *)DT_TI_STELLARIS_UART_4000C000_BASE_ADDRESS,
.sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ,
.sys_clk_freq = DT_TI_STELLARIS_UART_4000C000_CLOCKS_CLOCK_FREQUENCY,

#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = irq_config_func_0,
Expand Down Expand Up @@ -672,7 +672,7 @@ static void irq_config_func_1(struct device *port);

static struct uart_device_config uart_stellaris_dev_cfg_1 = {
.base = (u8_t *)DT_TI_STELLARIS_UART_4000D000_BASE_ADDRESS,
.sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ,
.sys_clk_freq = DT_TI_STELLARIS_UART_4000D000_CLOCKS_CLOCK_FREQUENCY,

#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = irq_config_func_1,
Expand Down Expand Up @@ -710,7 +710,7 @@ static void irq_config_func_2(struct device *port);

static const struct uart_device_config uart_stellaris_dev_cfg_2 = {
.base = (u8_t *)DT_TI_STELLARIS_UART_4000E000_BASE_ADDRESS,
.sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ,
.sys_clk_freq = DT_TI_STELLARIS_UART_4000E000_CLOCKS_CLOCK_FREQUENCY,

#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = irq_config_func_2,
Expand Down
10 changes: 8 additions & 2 deletions drivers/spi/spi_dw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -252,7 +252,8 @@ static int spi_dw_configure(const struct spi_dw_config *info,

if (!spi_dw_is_slave(spi)) {
/* Baud rate and Slave select, for master only */
write_baudr(SPI_DW_CLK_DIVIDER(config->frequency), info->regs);
write_baudr(SPI_DW_CLK_DIVIDER(info->clock_frequency,
config->frequency), info->regs);
write_ser(1 << config->slave, info->regs);
}

Expand All @@ -273,7 +274,8 @@ static int spi_dw_configure(const struct spi_dw_config *info,
LOG_DBG("Installed master config %p: freq %uHz (div = %u),"
" ws/dfs %u/%u, mode %u/%u/%u, slave %u",
config, config->frequency,
SPI_DW_CLK_DIVIDER(config->frequency),
SPI_DW_CLK_DIVIDER(info->clock_frequency,
config->frequency),
SPI_WORD_SIZE_GET(config->operation), spi->dfs,
(SPI_MODE_GET(config->operation) &
SPI_MODE_CPOL) ? 1 : 0,
Expand Down Expand Up @@ -535,6 +537,7 @@ struct spi_dw_data spi_dw_data_port_0 = {

const struct spi_dw_config spi_dw_config_0 = {
.regs = DT_SPI_0_BASE_ADDRESS,
.clock_frequency = DT_SPI_0_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS),
Expand Down Expand Up @@ -583,6 +586,7 @@ struct spi_dw_data spi_dw_data_port_1 = {

static const struct spi_dw_config spi_dw_config_1 = {
.regs = DT_SPI_1_BASE_ADDRESS,
.clock_frequency = DT_SPI_1_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_1_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS),
Expand Down Expand Up @@ -631,6 +635,7 @@ struct spi_dw_data spi_dw_data_port_2 = {

static const struct spi_dw_config spi_dw_config_2 = {
.regs = DT_SPI_2_BASE_ADDRESS,
.clock_frequency = DT_SPI_2_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS),
Expand Down Expand Up @@ -679,6 +684,7 @@ struct spi_dw_data spi_dw_data_port_3 = {

static const struct spi_dw_config spi_dw_config_3 = {
.regs = DT_SPI_3_BASE_ADDRESS,
.clock_frequency = DT_SPI_3_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS),
Expand Down
12 changes: 3 additions & 9 deletions drivers/spi/spi_dw.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ typedef void (*spi_dw_config_t)(void);
/* Private structures */
struct spi_dw_config {
u32_t regs;
u32_t clock_frequency;
#ifdef CONFIG_CLOCK_CONTROL
const char *clock_name;
void *clock_data;
Expand All @@ -42,15 +43,8 @@ struct spi_dw_data {

/* Helper macros */

#ifdef DT_SPI_DW_SPI_CLOCK
#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \
((DT_SPI_DW_SPI_CLOCK / ssi_clk_hz) & 0xFFFF)
/* provision for soc.h providing a clock that is different than CPU clock */
#else
#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \
((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / ssi_clk_hz) & 0xFFFF)
#endif

#define SPI_DW_CLK_DIVIDER(clock_freq, ssi_clk_hz) \
((clock_freq / ssi_clk_hz) & 0xFFFF)

#ifdef CONFIG_SPI_DW_ARC_AUX_REGS
#define Z_REG_READ(__sz) sys_in##__sz
Expand Down
2 changes: 1 addition & 1 deletion drivers/timer/arcv2_timer0.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@
#define MIN_DELAY 512
#define COUNTER_MAX 0xffffffff
#define TIMER_STOPPED 0x0
#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)

#define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
Expand Down
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