We need to make sure that __NVIC_PRIO_BITS & CONFIG_NUM_IRQ_PRIO_BITS
are set to the same value.  Add a simple build time check to ensure
this is the case.  This is to catch future cases of issues like
ZEP-2243.  This is a stop gap til we resolve ZEP-2262, which covers use
of both __NVIC_PRIO_BITS & CONFIG_NUM_IRQ_PRIO_BITS.

Signed-off-by: Kumar Gala <[email protected]>

Functionality of a pinmux driver is now a part of a regular
driver.

Signed-off-by: Shiksha Patel <[email protected]>

Clearing fields in the region descriptor attributes doesn't always have
the expected effect of revoking permissions. In the case of bus master
supervisor mode fields (MxSM), setting to zero actually enables read,
write, and execute access.

When we reworked handling of region descriptor 0, we inadvertently
enabled execution from RAM by clearing the MxSM fields and enabling the
descriptor. This caused samples/mpu_test run to throw a usage fault
instead of an MPU-triggered bus fault.

Fix this by setting all the MxSM fields to 2'b11, which gives supervisor
mode the same access as user mode.

Signed-off-by: Maureen Helm <[email protected]>

Correct code that allows to disable ERASE pin functionality
during boot.

Signed-off-by: Piotr Mienkowski <[email protected]>

The porting of the TI CC2650 SoC introduces the need to
write a specific configuration area (CCFG) at the end of the
flash. It is read by the bootloader ROM of the SoC.

For now, this is a quick hack and not a generic solution;
similar needs may arise with other hardware.

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>

We always have UART_IRQ_FLAGS set to 0, so just call IRQ_CONNECT with a
0 argument for the flags, and remove the UART_IRQ_FLAGS.  This is
towards support for using the driver on the TI CC2650.  (we add a
comment about that as well).

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>

L4 have 64 bits write access.
The cast to 64 bits data address in write_dword
requires 3 right shifts on i (byte index) else the
data taken are wrong for i different from 0

Signed-off-by: Michel Jaouen <[email protected]>

L4 write access requires 64 bits alignment
while L4 read access does not require any alignment.
To support specific check according to read/write,erase
a parameter is added to stm32_valid_range.

Signed-off-by: Michel Jaouen <[email protected]>

Update driver to use DTS-generated #defines for port names,
and not obsolete Kconfig variables.

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>

Add support in arch/arm/soc/ti_simplelink, along with support
for CC32xx SoC.

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>

Add support for TI's SensorTag board, which uses a CC2650 SoC.

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>

Add extra #defines in samples/drivers/gpio to test
TI SensorTag board.

Signed-off-by: Geoffrey Le Gourriérec <[email protected]>

Signed-off-by: Kumar Gala <[email protected]>

We define a variable to pickup a default for the bossa binary, however
we weren't using it.  Lets do so now.

Signed-off-by: Kumar Gala <[email protected]>

If we have more than one board of a given type we need to be able to
specify the board_id to select which specific board that the pyocd
command should target.  Introduce an environment variable PYOCD_BOARD_ID
to we can set that will get passed to the pyocd command that needs it.

Here's an example:

$ make -C samples/hello_world/ BOARD=frdm_k64f flash PYOCD_BOARD_ID=1234

Signed-off-by: Kumar Gala <[email protected]>

As there are multiple ways to flash or debug (pyOCD or openOCD) allow
the user to override the default.

Signed-off-by: Kumar Gala <[email protected]>

Allow to use an external debug adapter such as J-Link or ULINK
connected to a 20-pin JTAG header to flash the image. SWD is
the actual protocol used by the debug interface.

Signed-off-by: Piotr Mienkowski <[email protected]>

Current implementation of LL_SPI_TransmitData16 on F3/F7/L4 family
generates following warning:
"warning: dereferencing type-punned pointer will break strict-aliasing
rules [-Wstrict-aliasing]"
Besides being forbidden by rule, this cast is not needed, as register is
16 bits wide. Modification has been tested on L4 SoC.
stm32yyxx_ll_spi.h being included in soc.h file, warning is generated
at each compiled object, this commit allows a clean build.
This issue is referenced in ST and tracked under
reference  13359. Code will be updated on upcoming stm32cube updates.

Change-Id: I3ca54a81d849d4852eca86b52b6825b60e18b752
Signed-off-by: Erwan Gouriou <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>

Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>

Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>

Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>

Add a SPI master and slave driver for the L4, F4 and F3 STM SoCs families.

Change-Id: I1faf5c97f992c91eba852fd126e7d3b83158993d
Origin: Original
Signed-off-by: Neil Armstrong <[email protected]>
Tested-by: Lee Jones <[email protected]>

Add SPI pin for the nucleo_f401re pinmux.

Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>

Following implementation of LL based SPI driver,
add SPI support on nucleo_f334r8 board of STM32F3 series.

Change-Id: Ifbe39b1f2cecdd7db23be9c6943a914a155ebd77
Signed-off-by: Erwan Gouriou <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>

Signed-off-by: Neil Armstrong <[email protected]>

Signed-off-by: Neil Armstrong <[email protected]>

Signed-off-by: Neil Armstrong <[email protected]>