Timer rewrite phase 3: drivers

drivers/timer/Kconfig

@@ -16,6 +16,7 @@ config HPET_TIMER
 	select IOAPIC
 	select LOAPIC
 	select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
+	select TICKLESS_CAPABLE
 	help
 	  This option selects High Precision Event Timer (HPET) as a
 	  system timer.
@@ -132,6 +133,7 @@ config CORTEX_M_SYSTICK
 	bool "Cortex-M SYSTICK timer"
 	default y
 	depends on CPU_HAS_SYSTICK
+	select TICKLESS_CAPABLE
 	help
 	  This module implements a kernel device driver for the Cortex-M processor
 	  SYSTICK timer and provides the standard "system clock driver" interfaces.
@@ -150,6 +152,7 @@ config NRF_RTC_TIMER
 	bool "nRF Real Time Counter (NRF_RTC1) Timer"
 	default y
 	depends on CLOCK_CONTROL_NRF5
+	select TICKLESS_CAPABLE
 	help
 	  This module implements a kernel device driver for the nRF Real Time
 	  Counter NRF_RTC1 and provides the standard "system clock driver"
@@ -166,6 +169,7 @@ config PULPINO_TIMER
 config RISCV_MACHINE_TIMER
 	bool "RISCV Machine Timer"
 	depends on SOC_FAMILY_RISCV_PRIVILEGE
+	select TICKLESS_CAPABLE
 	help
 	  This module implements a kernel device driver for the generic RISCV machine
 	  timer driver. It provides the standard "system clock driver" interfaces.
@@ -182,43 +186,23 @@ config XTENSA_TIMER
 	bool "Xtensa timer support"
 	depends on XTENSA
 	default y
+	select TICKLESS_CAPABLE
 	help
-	  This module implements a kernel device driver for the Xtensa processor and
-	  provides the standard "system clock driver" interfaces.
-	  If unchecked, no timer will be used.
-	  If checked it will use either an internal timer (default option) or an
-	  external timer. In that case one shall unselect XTENSA_INTERNAL_TIMER and
-	  define XTENSA_TIMER_IRQ and XTENSA_TIMER_IRQ_PRIORITY.
+	  Enables a system timer driver for Xtensa based on the CCOUNT
+	  and CCOMPARE special registers.
 
-config XTENSA_INTERNAL_TIMER
-	bool "Xtensa internal timer"
-	depends on XTENSA_TIMER
-	default y
-	help
-	  This module implements a kernel device driver for the Xtensa processor
-	  internal timer and provides the standard "system clock driver" interfaces.
-	  If unchecked, an external timer will be used. It will rely on a tick
-	  interrupt connected to an IRQ line. In this case one shall define
-	  both XTENSA_TIMER_IRQ and XTENSA_TIMER_IRQ_PRIORITY.
-
-config XTENSA_TIMER_IRQ
-	int "Xtensa external timer interrupt number"
-	depends on XTENSA_TIMER && !XTENSA_INTERNAL_TIMER
-	range -1 31
-	default -1
-	help
-	  This is the number of interrupt line used by the external timer.
-	  The special value of -1 allows using the internal timer in order to
-	  emulate an external timer. This is generally useful for running the project on
-	  a simulator	where it is hard to emulate an external interrupt.
-
-config XTENSA_TIMER_IRQ_PRIORITY
-	int "Xtensa external timer interrupt priority"
-	depends on XTENSA_TIMER && !XTENSA_INTERNAL_TIMER
-	range 1 6
+config XTENSA_TIMER_ID
+	int "System timer CCOMPAREn register index"
 	default 1
+	depends on XTENSA_TIMER
 	help
-	  This is the priority of interrupt line.
+	  Index of the CCOMPARE register (and associated interrupt)
+	  used for the system timer.  Xtensa CPUs have hard-configured
+	  interrupt priorities associated with each timer, and some of
+	  them can be unmaskable (and thus not usable by OS code that
+	  need synchronization, like the timer subsystem!).  Choose
+	  carefully.  Generally you want the timer with the highest
+	  priority maskable interrupt.
 
 config SYSTEM_CLOCK_DISABLE
 	bool "API to disable system clock"
@@ -242,4 +226,30 @@ config SYSTEM_CLOCK_INIT_PRIORITY
 	  the clock to be running already, you should let the default value as it
 	  is (0).
 
+config TICKLESS_CAPABLE
+	bool "Timer driver supports tickless operation"
+	help
+	  Timer drivers should select this flag if they are capable of
+	  supporting tickless operation.  That is, a call to
+	  z_clock_set_timeout() with a number of ticks greater than
+	  one should be expected not to produce a call to
+	  z_clock_announce() (really, not to produce an interrupt at
+	  all) until the specified expiration.
+
+config QEMU_TICKLESS_WORKAROUND
+	bool "Disable tickless on qemu due to asynchrony bug"
+	depends on QEMU_TARGET && TICKLESS_KERNEL
+	help
+	  Qemu (without -icount) has trouble keeping time when the
+	  host process needs to timeshare.  The host OS will routinely
+	  schedule out a process at timescales equivalent to the guest
+	  tick rate.  With traditional ticks delivered regularly by
+	  the hardware, that's mostly OK as it looks like a late
+	  interrupt.  But in tickless mode, the driver needs some CPU
+	  in order to schedule the tick in the first place.  If that
+	  gets delayed across a tick boundary, time gets wonky.  This
+	  tunable is a hint to the driver to disable tickless
+	  accounting on qemu.  Use it only on tests that are known to
+	  have problems.
+
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