drivers: memc: Introduce i.MX RT FlexSPI HyperRAM driver

Add the FlexSPI HyperBUS driver to support HyperRAM external
devices.

Signed-off-by: Pieter De Gendt <[email protected]>

drivers/memc/CMakeLists.txt

@@ -5,3 +5,4 @@ zephyr_sources_ifdef(CONFIG_MEMC_STM32_SDRAM memc_stm32_sdram.c)
 zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_SDRAM SECTIONS memc_stm32_sdram.ld)
 
 zephyr_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c)
+zephyr_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_HYPERRAM memc_mcux_flexspi_hyperram.c)

drivers/memc/Kconfig.mcux

@@ -4,6 +4,10 @@
 
 if HAS_MCUX_FLEXSPI
 
+config MEMC_MCUX_FLEXSPI_HYPERRAM
+	bool "MCUX FlexSPI HyperRAM driver"
+	select MEMC_MCUX_FLEXSPI
+
 config MEMC_MCUX_FLEXSPI
 	bool
 

drivers/memc/memc_mcux_flexspi.c

@@ -21,6 +21,7 @@ struct memc_flexspi_config {
 	bool ahb_prefetch;
 	bool ahb_read_addr_opt;
 	bool combination_mode;
+	bool sck_differential_clock;
 	flexspi_read_sample_clock_t rx_sample_clock;
 };
 
@@ -113,6 +114,7 @@ static int memc_flexspi_init(const struct device *dev)
 	flexspi_config.ahbConfig.enableAHBPrefetch = config->ahb_prefetch;
 	flexspi_config.ahbConfig.enableReadAddressOpt = config->ahb_read_addr_opt;
 	flexspi_config.enableCombination = config->combination_mode;
+	flexspi_config.enableSckBDiffOpt = config->sck_differential_clock;
 	flexspi_config.rxSampleClock = config->rx_sample_clock;
 
 	FLEXSPI_Init(config->base, &flexspi_config);
@@ -130,6 +132,7 @@ static int memc_flexspi_init(const struct device *dev)
 		.ahb_prefetch = DT_INST_PROP(n, ahb_prefetch),		\
 		.ahb_read_addr_opt = DT_INST_PROP(n, ahb_read_addr_opt),\
 		.combination_mode = DT_INST_PROP(n, combination_mode),	\
+		.sck_differential_clock = DT_INST_PROP(n, sck_differential_clock),	\
 		.rx_sample_clock = DT_INST_PROP(n, rx_clock_source),	\
 	};								\
 									\

drivers/memc/memc_mcux_flexspi_hyperram.c

@@ -0,0 +1,191 @@
+/*
+ * Copyright 2021 Basalte bv
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT   nxp_imx_flexspi_hyperram
+
+#include <logging/log.h>
+#include <sys/util.h>
+
+#include "memc_mcux_flexspi.h"
+
+LOG_MODULE_DECLARE(memc_flexspi, CONFIG_MEMC_LOG_LEVEL);
+
+enum {
+	READ_DATA,
+	WRITE_DATA,
+	READ_REG,
+	WRITE_REG,
+};
+
+struct memc_flexspi_hyperram_config {
+	char *controller_label;
+	flexspi_port_t port;
+	flexspi_device_config_t config;
+};
+
+struct memc_flexspi_hyperram_data {
+	const struct device *controller;
+};
+
+static const uint32_t memc_flexspi_hyperram_lut[][4] = {
+	/* Read Data */
+	[READ_DATA] = {
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR,             kFLEXSPI_8PAD, 0xA0,
+				kFLEXSPI_Command_RADDR_DDR,       kFLEXSPI_8PAD, 0x18),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR,       kFLEXSPI_8PAD, 0x10,
+				kFLEXSPI_Command_DUMMY_RWDS_DDR,  kFLEXSPI_8PAD, 0x06),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR,        kFLEXSPI_8PAD, 0x04,
+				kFLEXSPI_Command_STOP,            kFLEXSPI_1PAD, 0x00),
+	},
+
+	/* Write Data */
+	[WRITE_DATA] = {
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR,             kFLEXSPI_8PAD, 0x20,
+				kFLEXSPI_Command_RADDR_DDR,       kFLEXSPI_8PAD, 0x18),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR,       kFLEXSPI_8PAD, 0x10,
+				kFLEXSPI_Command_DUMMY_RWDS_DDR,  kFLEXSPI_8PAD, 0x06),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR,       kFLEXSPI_8PAD, 0x04,
+				kFLEXSPI_Command_STOP,            kFLEXSPI_1PAD, 0x00),
+	},
+
+	/* Read Register */
+	[READ_REG] = {
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR,             kFLEXSPI_8PAD, 0xE0,
+				kFLEXSPI_Command_RADDR_DDR,       kFLEXSPI_8PAD, 0x18),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR,       kFLEXSPI_8PAD, 0x10,
+				kFLEXSPI_Command_DUMMY_RWDS_DDR,  kFLEXSPI_8PAD, 0x06),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR,        kFLEXSPI_8PAD, 0x04,
+				kFLEXSPI_Command_STOP,            kFLEXSPI_1PAD, 0x00),
+	},
+
+	/* Write Register */
+	[WRITE_REG] = {
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR,             kFLEXSPI_8PAD, 0x60,
+				kFLEXSPI_Command_RADDR_DDR,       kFLEXSPI_8PAD, 0x18),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR,       kFLEXSPI_8PAD, 0x10,
+				kFLEXSPI_Command_DUMMY_RWDS_DDR,  kFLEXSPI_8PAD, 0x06),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR,       kFLEXSPI_8PAD, 0x04,
+				kFLEXSPI_Command_STOP,            kFLEXSPI_1PAD, 0x00),
+	},
+};
+
+static int memc_flexspi_hyperram_get_vendor_id(const struct device *dev,
+						uint16_t *vendor_id)
+{
+	const struct memc_flexspi_hyperram_config *config = dev->config;
+	struct memc_flexspi_hyperram_data *data = dev->data;
+	uint32_t buffer = 0;
+	int ret;
+
+	flexspi_transfer_t transfer = {
+		.deviceAddress = 0,
+		.port = config->port,
+		.cmdType = kFLEXSPI_Read,
+		.SeqNumber = 1,
+		.seqIndex = READ_REG,
+		.data = &buffer,
+		.dataSize = 4,
+	};
+
+	LOG_DBG("Reading id");
+
+	ret = memc_flexspi_transfer(data->controller, &transfer);
+	*vendor_id = buffer & 0xffff;
+
+	return ret;
+}
+
+static int memc_flexspi_hyperram_init(const struct device *dev)
+{
+	const struct memc_flexspi_hyperram_config *config = dev->config;
+	struct memc_flexspi_hyperram_data *data = dev->data;
+	uint16_t vendor_id;
+
+	data->controller = device_get_binding(config->controller_label);
+	if (data->controller == NULL) {
+		LOG_ERR("Could not find controller");
+		return -EINVAL;
+	}
+
+	if (memc_flexspi_set_device_config(data->controller, &config->config,
+					   config->port)) {
+		LOG_ERR("Could not set device configuration");
+		return -EINVAL;
+	}
+
+	if (memc_flexspi_update_lut(data->controller, 0,
+				    (const uint32_t *) memc_flexspi_hyperram_lut,
+				    sizeof(memc_flexspi_hyperram_lut) / 4)) {
+		LOG_ERR("Could not update lut");
+		return -EINVAL;
+	}
+
+	memc_flexspi_reset(data->controller);
+
+	if (memc_flexspi_hyperram_get_vendor_id(dev, &vendor_id)) {
+		LOG_ERR("Could not read vendor id");
+		return -EIO;
+	}
+	LOG_DBG("Vendor id: 0x%0x", vendor_id);
+
+	return 0;
+}
+
+#define CONCAT3(x, y, z) x ## y ## z
+
+#define CS_INTERVAL_UNIT(unit) \
+	CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
+
+#define AHB_WRITE_WAIT_UNIT(unit) \
+	CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
+
+#define MEMC_FLEXSPI_DEVICE_CONFIG(n)					\
+	{								\
+		.flexspiRootClk = MHZ(332),				\
+		.isSck2Enabled = false,					\
+		.flashSize = DT_INST_PROP(n, size) / 8 / KB(1),		\
+		.CSIntervalUnit =					\
+			CS_INTERVAL_UNIT(				\
+				DT_INST_PROP(n, cs_interval_unit)),	\
+		.CSInterval = DT_INST_PROP(n, cs_interval),		\
+		.CSHoldTime = DT_INST_PROP(n, cs_hold_time),		\
+		.CSSetupTime = DT_INST_PROP(n, cs_setup_time),		\
+		.dataValidTime = DT_INST_PROP(n, data_valid_time),	\
+		.columnspace = DT_INST_PROP(n, column_space),		\
+		.enableWordAddress = DT_INST_PROP(n, word_addressable),	\
+		.AWRSeqIndex = WRITE_DATA,				\
+		.AWRSeqNumber = 1,					\
+		.ARDSeqIndex = READ_DATA,				\
+		.ARDSeqNumber = 1,					\
+		.AHBWriteWaitUnit =					\
+			AHB_WRITE_WAIT_UNIT(				\
+				DT_INST_PROP(n, ahb_write_wait_unit)),	\
+		.AHBWriteWaitInterval =					\
+			DT_INST_PROP(n, ahb_write_wait_interval),	\
+		.enableWriteMask = true,				\
+	}								\
+
+#define MEMC_FLEXSPI_HYPERRAM(n)				  \
+	static const struct memc_flexspi_hyperram_config	  \
+		memc_flexspi_hyperram_config_##n = {		  \
+		.controller_label = DT_INST_BUS_LABEL(n),	  \
+		.port = DT_INST_REG_ADDR(n),			  \
+		.config = MEMC_FLEXSPI_DEVICE_CONFIG(n),	  \
+	};							  \
+								  \
+	static struct memc_flexspi_hyperram_data		  \
+		memc_flexspi_hyperram_data_##n;			  \
+								  \
+	DEVICE_DT_INST_DEFINE(n,				  \
+			      memc_flexspi_hyperram_init,	  \
+			      device_pm_control_nop,		  \
+			      &memc_flexspi_hyperram_data_##n,	  \
+			      &memc_flexspi_hyperram_config_##n,  \
+			      POST_KERNEL,			  \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
+			      NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(MEMC_FLEXSPI_HYPERRAM)

dts/bindings/mtd/nxp,imx-flexspi-hyperram.yaml

@@ -0,0 +1,8 @@
+# Copyright 2021 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI HyperRAM
+
+compatible: "nxp,imx-flexspi-hyperram"
+
+include: nxp,imx-flexspi-device.yaml

dts/bindings/spi/nxp,imx-flexspi.yaml

@@ -48,6 +48,13 @@ properties:
         Combine port A and port B data pins to support octal mode access by
         setting register field MCR0[COMBINATIONEN].
 
+    sck-differential-clock:
+      type: boolean
+      required: false
+      description: |
+        Enable/disable SCKB pad use as SCKA differential clock output,
+        when enabled, Port B flash access is not available.
+
     rx-clock-source:
       type: int
       required: false