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Deal with input register aliasing. #1473

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@ltratt ltratt commented Nov 21, 2024

NB: do not merge until Edd has confirmed this works!

Currently our register allocator assumes that SSA variables can't alias. This is true for the parts under our control -- but isn't true of the inputs to a trace! For example both %0 and %1 might come from RAX. This caused a panic in the register allocator.

I'd noted the problem in #1449 but thought it happened rarely. Edd noticed that it happens in other, more common situations (including as a result of common subexpression elimination), including in a yklua benchmark, and created a test for it.

This commit is a "quick fix" (it's not pretty, or efficient): when we spot aliasing, we spill aliased variables onto the stack, implicitly dealiasing them. In other words, we avoid having to think about aliasing in the main bulk of the register allocator at the expense of having to spill (and potentially unspill) values unnecessarily.

let op1 = m.push_and_make_operand(ti_inst.clone().into()).unwrap();
let op2 = m.push_and_make_operand(ti_inst.into()).unwrap();

// Then a use of those two variable simealtaneously will make a debug_assertion in the
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Probably need to revise this comment, since we've fixed the assertion failure.

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Fixed in 7d45fa7.

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Please squash,

Currently our register allocator assumes that SSA variables can't alias.
This is true for the parts under our control -- but isn't true of the
inputs to a trace! For example both `%0` and `%1` might come from `RAX`.
This caused a panic in the register allocator.

I'd noted the problem in ykjit#1449 but
thought it happened rarely. Edd noticed that it happens in other, more
common situations (including as a result of common subexpression
elimination), including in a yklua benchmark, and created a test for it.

This commit is a "quick fix" (it's not pretty, or efficient): when we
spot aliasing, we spill aliased variables onto the stack, implicitly
dealiasing them. In other words, we avoid having to think about aliasing
in the main bulk of the register allocator at the expense of having to
spill (and potentially unspill) values unnecessarily.

Co-authored-by: Edd Barrett <[email protected]>
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ltratt commented Nov 21, 2024

Squashed.

@ptersilie ptersilie added this pull request to the merge queue Nov 21, 2024
@github-merge-queue github-merge-queue bot removed this pull request from the merge queue due to failed status checks Nov 21, 2024
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ltratt commented Nov 21, 2024

@ptersilie I think this might be a preexisting bug, and it might be worth trying again. If not, @vext01 thinks he's seen this bug before.

@ptersilie ptersilie added this pull request to the merge queue Nov 21, 2024
@github-merge-queue github-merge-queue bot removed this pull request from the merge queue due to failed status checks Nov 21, 2024
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3 participants