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Hack around JIT IR parser limitations in unit testing.
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vext01 committed Oct 21, 2024
1 parent 3b79aa5 commit 40fc3dd
Showing 1 changed file with 10 additions and 0 deletions.
10 changes: 10 additions & 0 deletions ykrt/src/compile/jitc_yk/jit_ir/parser.rs
Original file line number Diff line number Diff line change
Expand Up @@ -319,15 +319,25 @@ impl<'lexer, 'input: 'lexer> JITIRParser<'lexer, 'input, '_> {
match self.m.type_(type_) {
Ty::Void => unreachable!(),
Ty::Integer(_) | Ty::Ptr | Ty::Func(_) => {
if gp_reg_off == 15 {
panic!("out of gp registers");
}
self.m.push_tiloc(yksmp::Location::Register(
gp_reg_off,
u16::try_from(size).unwrap(),
0,
vec![],
));
gp_reg_off += 1;
// FIXME: gross hack to avoid allocating RBP/RSP.
while gp_reg_off == 6 || gp_reg_off == 7 {
gp_reg_off += 1;
}
}
Ty::Float(_) => {
if fp_reg_off == 32 {
panic!("out of fp regisers");
}
self.m.push_tiloc(yksmp::Location::Register(
fp_reg_off,
u16::try_from(size).unwrap(),
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