Skip to content

yasir-javed/bram_xilinxise

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

3 Commits
 
 
 
 
 
 
 
 

Repository files navigation

Xilinx FPGA Block RAM

Xilinx ISE provides coding examples template to generate Block RAMs. It normally requires changing variable names in the template code every time one wants to use BRAMs. This code is a parametrized wrapper based on template code that allows to generate BRAM of any size and if required provide initialization file for BRAM. Test bench tests the BRAM with some simple sequential reads and writes.

Following video explains how the code was created and how to use it

FPGA BRAM verilog code

Similar steps can be used to generate parametrized BRAM module for Xilinx Vivado

About

No description, website, or topics provided.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published