feat: updating from newer svd2rust (#92)

Co-authored-by: lucasbrendel <[email protected]>

src/can.rs

@@ -1,149 +1,139 @@
 #[repr(C)]
 #[doc = "Register block"]
 pub struct RegisterBlock {
-    clc: Clc,
+    clc: CLC,
     _reserved1: [u8; 0x04],
-    id: Id,
-    fdr: Fdr,
+    id: ID,
+    fdr: FDR,
     _reserved3: [u8; 0xf0],
-    list: [List; 8],
+    list: [LIST; 8],
     _reserved4: [u8; 0x20],
-    mspnd: [Mspnd; 8],
+    mspnd: [MSPND; 8],
     _reserved5: [u8; 0x20],
-    msid: [Msid; 8],
+    msid: [MSID; 8],
     _reserved6: [u8; 0x20],
-    msimask: Msimask,
-    panctr: Panctr,
-    mcr: Mcr,
-    mitr: Mitr,
+    msimask: MSIMASK,
+    panctr: PANCTR,
+    mcr: MCR,
+    mitr: MITR,
 }
 impl RegisterBlock {
     #[doc = "0x00 - CAN Clock Control Register"]
     #[inline(always)]
-    pub const fn clc(&self) -> &Clc {
+    pub const fn clc(&self) -> &CLC {
         &self.clc
     }
     #[doc = "0x08 - Module Identification Register"]
     #[inline(always)]
-    pub const fn id(&self) -> &Id {
+    pub const fn id(&self) -> &ID {
         &self.id
     }
     #[doc = "0x0c - CAN Fractional Divider Register"]
     #[inline(always)]
-    pub const fn fdr(&self) -> &Fdr {
+    pub const fn fdr(&self) -> &FDR {
         &self.fdr
     }
     #[doc = "0x100..0x120 - List Register"]
     #[inline(always)]
-    pub const fn list(&self, n: usize) -> &List {
+    pub const fn list(&self, n: usize) -> &LIST {
         &self.list[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x100..0x120 - List Register"]
     #[inline(always)]
-    pub fn list_iter(&self) -> impl Iterator<Item = &List> {
+    pub fn list_iter(&self) -> impl Iterator<Item = &LIST> {
         self.list.iter()
     }
     #[doc = "0x140..0x160 - Message Pending Register"]
     #[inline(always)]
-    pub const fn mspnd(&self, n: usize) -> &Mspnd {
+    pub const fn mspnd(&self, n: usize) -> &MSPND {
         &self.mspnd[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x140..0x160 - Message Pending Register"]
     #[inline(always)]
-    pub fn mspnd_iter(&self) -> impl Iterator<Item = &Mspnd> {
+    pub fn mspnd_iter(&self) -> impl Iterator<Item = &MSPND> {
         self.mspnd.iter()
     }
     #[doc = "0x180..0x1a0 - Message Index Register"]
     #[inline(always)]
-    pub const fn msid(&self, n: usize) -> &Msid {
+    pub const fn msid(&self, n: usize) -> &MSID {
         &self.msid[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x180..0x1a0 - Message Index Register"]
     #[inline(always)]
-    pub fn msid_iter(&self) -> impl Iterator<Item = &Msid> {
+    pub fn msid_iter(&self) -> impl Iterator<Item = &MSID> {
         self.msid.iter()
     }
     #[doc = "0x1c0 - Message Index Mask Register"]
     #[inline(always)]
-    pub const fn msimask(&self) -> &Msimask {
+    pub const fn msimask(&self) -> &MSIMASK {
         &self.msimask
     }
     #[doc = "0x1c4 - Panel Control Register"]
     #[inline(always)]
-    pub const fn panctr(&self) -> &Panctr {
+    pub const fn panctr(&self) -> &PANCTR {
         &self.panctr
     }
     #[doc = "0x1c8 - Module Control Register"]
     #[inline(always)]
-    pub const fn mcr(&self) -> &Mcr {
+    pub const fn mcr(&self) -> &MCR {
         &self.mcr
     }
     #[doc = "0x1cc - Module Interrupt Trigger Register"]
     #[inline(always)]
-    pub const fn mitr(&self) -> &Mitr {
+    pub const fn mitr(&self) -> &MITR {
         &self.mitr
     }
 }
 #[doc = "CLC (rw) register accessor: CAN Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clc`]
 module"]
-#[doc(alias = "CLC")]
-pub type Clc = crate::Reg<clc::ClcSpec>;
+pub type CLC = crate::Reg<clc::CLC_SPEC>;
 #[doc = "CAN Clock Control Register"]
 pub mod clc;
 #[doc = "ID (r) register accessor: Module Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`]
 module"]
-#[doc(alias = "ID")]
-pub type Id = crate::Reg<id::IdSpec>;
+pub type ID = crate::Reg<id::ID_SPEC>;
 #[doc = "Module Identification Register"]
 pub mod id;
 #[doc = "FDR (rw) register accessor: CAN Fractional Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fdr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdr`]
 module"]
-#[doc(alias = "FDR")]
-pub type Fdr = crate::Reg<fdr::FdrSpec>;
+pub type FDR = crate::Reg<fdr::FDR_SPEC>;
 #[doc = "CAN Fractional Divider Register"]
 pub mod fdr;
 #[doc = "LIST (r) register accessor: List Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`list::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@list`]
 module"]
-#[doc(alias = "LIST")]
-pub type List = crate::Reg<list::ListSpec>;
+pub type LIST = crate::Reg<list::LIST_SPEC>;
 #[doc = "List Register"]
 pub mod list;
 #[doc = "MSPND (rw) register accessor: Message Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mspnd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mspnd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mspnd`]
 module"]
-#[doc(alias = "MSPND")]
-pub type Mspnd = crate::Reg<mspnd::MspndSpec>;
+pub type MSPND = crate::Reg<mspnd::MSPND_SPEC>;
 #[doc = "Message Pending Register"]
 pub mod mspnd;
 #[doc = "MSID (r) register accessor: Message Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msid`]
 module"]
-#[doc(alias = "MSID")]
-pub type Msid = crate::Reg<msid::MsidSpec>;
+pub type MSID = crate::Reg<msid::MSID_SPEC>;
 #[doc = "Message Index Register"]
 pub mod msid;
 #[doc = "MSIMASK (rw) register accessor: Message Index Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msimask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msimask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msimask`]
 module"]
-#[doc(alias = "MSIMASK")]
-pub type Msimask = crate::Reg<msimask::MsimaskSpec>;
+pub type MSIMASK = crate::Reg<msimask::MSIMASK_SPEC>;
 #[doc = "Message Index Mask Register"]
 pub mod msimask;
 #[doc = "PANCTR (rw) register accessor: Panel Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`panctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`panctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@panctr`]
 module"]
-#[doc(alias = "PANCTR")]
-pub type Panctr = crate::Reg<panctr::PanctrSpec>;
+pub type PANCTR = crate::Reg<panctr::PANCTR_SPEC>;
 #[doc = "Panel Control Register"]
 pub mod panctr;
 #[doc = "MCR (rw) register accessor: Module Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
 module"]
-#[doc(alias = "MCR")]
-pub type Mcr = crate::Reg<mcr::McrSpec>;
+pub type MCR = crate::Reg<mcr::MCR_SPEC>;
 #[doc = "Module Control Register"]
 pub mod mcr;
 #[doc = "MITR (w) register accessor: Module Interrupt Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mitr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mitr`]
 module"]
-#[doc(alias = "MITR")]
-pub type Mitr = crate::Reg<mitr::MitrSpec>;
+pub type MITR = crate::Reg<mitr::MITR_SPEC>;
 #[doc = "Module Interrupt Trigger Register"]
 pub mod mitr;

src/can/clc.rs

@@ -1,70 +1,70 @@
 #[doc = "Register `CLC` reader"]
-pub type R = crate::R<ClcSpec>;
+pub type R = crate::R<CLC_SPEC>;
 #[doc = "Register `CLC` writer"]
-pub type W = crate::W<ClcSpec>;
+pub type W = crate::W<CLC_SPEC>;
 #[doc = "Field `DISR` reader - Module Disable Request Bit"]
-pub type DisrR = crate::BitReader;
+pub type DISR_R = crate::BitReader;
 #[doc = "Field `DISR` writer - Module Disable Request Bit"]
-pub type DisrW<'a, REG> = crate::BitWriter<'a, REG>;
+pub type DISR_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `DISS` reader - Module Disable Status Bit"]
-pub type DissR = crate::BitReader;
+pub type DISS_R = crate::BitReader;
 #[doc = "Field `EDIS` reader - Sleep Mode Enable Control"]
-pub type EdisR = crate::BitReader;
+pub type EDIS_R = crate::BitReader;
 #[doc = "Field `EDIS` writer - Sleep Mode Enable Control"]
-pub type EdisW<'a, REG> = crate::BitWriter<'a, REG>;
+pub type EDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `SBWE` writer - Module Suspend Bit Write Enable for OCDS"]
-pub type SbweW<'a, REG> = crate::BitWriter<'a, REG>;
+pub type SBWE_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bit 0 - Module Disable Request Bit"]
     #[inline(always)]
-    pub fn disr(&self) -> DisrR {
-        DisrR::new((self.bits & 1) != 0)
+    pub fn disr(&self) -> DISR_R {
+        DISR_R::new((self.bits & 1) != 0)
     }
     #[doc = "Bit 1 - Module Disable Status Bit"]
     #[inline(always)]
-    pub fn diss(&self) -> DissR {
-        DissR::new(((self.bits >> 1) & 1) != 0)
+    pub fn diss(&self) -> DISS_R {
+        DISS_R::new(((self.bits >> 1) & 1) != 0)
     }
     #[doc = "Bit 3 - Sleep Mode Enable Control"]
     #[inline(always)]
-    pub fn edis(&self) -> EdisR {
-        EdisR::new(((self.bits >> 3) & 1) != 0)
+    pub fn edis(&self) -> EDIS_R {
+        EDIS_R::new(((self.bits >> 3) & 1) != 0)
     }
 }
 impl W {
     #[doc = "Bit 0 - Module Disable Request Bit"]
     #[inline(always)]
     #[must_use]
-    pub fn disr(&mut self) -> DisrW<ClcSpec> {
-        DisrW::new(self, 0)
+    pub fn disr(&mut self) -> DISR_W<CLC_SPEC> {
+        DISR_W::new(self, 0)
     }
     #[doc = "Bit 3 - Sleep Mode Enable Control"]
     #[inline(always)]
     #[must_use]
-    pub fn edis(&mut self) -> EdisW<ClcSpec> {
-        EdisW::new(self, 3)
+    pub fn edis(&mut self) -> EDIS_W<CLC_SPEC> {
+        EDIS_W::new(self, 3)
     }
     #[doc = "Bit 4 - Module Suspend Bit Write Enable for OCDS"]
     #[inline(always)]
     #[must_use]
-    pub fn sbwe(&mut self) -> SbweW<ClcSpec> {
-        SbweW::new(self, 4)
+    pub fn sbwe(&mut self) -> SBWE_W<CLC_SPEC> {
+        SBWE_W::new(self, 4)
     }
 }
 #[doc = "CAN Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct ClcSpec;
-impl crate::RegisterSpec for ClcSpec {
+pub struct CLC_SPEC;
+impl crate::RegisterSpec for CLC_SPEC {
     type Ux = u32;
 }
 #[doc = "`read()` method returns [`clc::R`](R) reader structure"]
-impl crate::Readable for ClcSpec {}
+impl crate::Readable for CLC_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`clc::W`](W) writer structure"]
-impl crate::Writable for ClcSpec {
+impl crate::Writable for CLC_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLC to value 0x03"]
-impl crate::Resettable for ClcSpec {
+impl crate::Resettable for CLC_SPEC {
     const RESET_VALUE: u32 = 0x03;
 }