fix case when offset is odd and size is even (apache#3643)

wweic · Aug 9, 2019 · c84f6e7 · c84f6e7
1 parent 8cafc1b
commit c84f6e7
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
@@ -76,7 +76,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
   val xcnt = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len))
   val xlen = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len))
   val xrem = Reg(chiselTypeOf(dec.xsize))
-  val xsize = dec.xsize(0) + (dec.xsize >> log2Ceil(numUop)) - 1.U
+  val xsize =  (dec.xsize >> log2Ceil(numUop)) + dec.xsize(0) + (dec.sram_offset % 2.U) - 1.U
   val xmax = (1 << mp.lenBits).U
   val xmax_bytes = ((1 << mp.lenBits)*mp.dataBits/8).U