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RISC-V 64 ASM: Add Poly1305 implementation #7873

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merged 1 commit into from
Aug 15, 2024

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SparkiDev
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Description

Implementation using standard and vector instructions.

Testing

./configure '--disable-shared' '--enable-chacha' '--enable-poly1305' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm'
./configure '--disable-shared' '--enable-chacha' '--enable-poly1305' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm=zv'

Checklist

  • added tests
  • updated/added doxygen
  • updated appropriate READMEs
  • Updated manual and documentation

Implementation using standard and vector instructions.
@SparkiDev SparkiDev assigned SparkiDev and wolfSSL-Bot and unassigned SparkiDev Aug 15, 2024
@SparkiDev SparkiDev requested a review from wolfSSL-Bot August 15, 2024 04:24
@dgarske
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dgarske commented Aug 15, 2024

HiFive Unmatched 1.2GHz:

Using ./configure --enable-riscv-asm:
With PR: POLY1305 280 MiB took 1.011 seconds, 276.835 MiB/s
With master: POLY1305 200 MiB took 1.009 seconds, 198.262 MiB/s

@dgarske dgarske merged commit 1190d1b into wolfSSL:master Aug 15, 2024
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3 participants