PYNQ projects using HLS and HDL IPs.
pynq folder provide a simple example using AXI4-Lite with and adder IP created in VHDL and other example using AXI4-Stream interface with AXI4-Stream FIFO.
The .ipynb files shows the deployment of the examples in the PYNQ-Z2 board using jupyter notebook.
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PYNQ projects using HLS and HDL IPs
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wesleygrignani/pynq_projects
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