custom mdc processor for two 8bits input.
The following project was created using the RTL method, first starting by a C-Level code for a mdc function:
The algorithm describes the behavior of the mdc function with control signals and variables to be created. Starting from the C code, we could implement our fist view of a High-Level state machine in order to organize what will happen in each state for the mdc algorithm.
With the High-Level state machine, we can now create our first view of the datapath, creating the necessary blocks to perform the desired calculations as seen in the High-Level state machine.
This image of the datapath help us to know with blocks we need to create to perform the desired calculations and give us the first view of the control signals that we are going to need to control these blocks, and then we can create our Finite State Machine with all controls needed to perform each operation in each state as seen in the previous High-Level state machine.
This Finite State Machine will be used to start our code phase in VHDL and is very important because we need to know which control signal we will need to control the blocks in the datapath as well as enable or disable these control signals at a specific state as we seen in the Finite State Machine. This is why is so important to create these steps very carefully.