Fix, test 4 passes

wchen329 · Dec 10, 2018 · 09a37bc · 09a37bc
1 parent 43b94bf
commit 09a37bc
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Showing 2 changed files with 24 additions and 3 deletions.
diff --git a/p3/cpu.v b/p3/cpu.v
@@ -103,7 +103,7 @@ module cpu(clk, rst_n, hlt, pc);
 
 
     PipelineRegister idex(
-        .clk(clk), .rst(rst), .we(~mem_miss_stall), .flush(stall),
+        .clk(clk), .rst(rst), .we(~mem_miss_stall), .flush(stall & ~mem_miss_stall),
         .hlt_in(id_hlt), .hlt_ou(ex_hlt),
         .RFwe_in(id_RFwe), .RFwe_ou(ex_RFwe),
         .RFdst_in(id_RFdst), .RFdst_ou(ex_RFdst),
@@ -136,6 +136,26 @@ module cpu(clk, rst_n, hlt, pc);
     CLAdder16 add1(ex_pc, 16'h0002, ex_pcplus2);
     assign ex_resultToPR = (ex_inst[15:12]==4'b1110) ? ex_pcplus2 : ex_aluout;
 
+    // Enable special MEM-EX forwarding path for stores only. It boils down to the following conditions:
+	// First,  storing?
+	// is the Register number storing non 0?
+	// is the Register being stored the same as the one the store data read from?
+	// Then FORWARD.
+    wire ex_mem_xx_sw;
+    wire [15:0] mem_RFout2_in;
+
+    assign ex_mem_xx_sw = ex_inst[15:12] == 4'b1001 ?
+				wb_RFwe == 1 ?
+					wb_RFdst != 4'b000 ?
+						ex_RFsrc2 == wb_RFdst?
+							1'b1
+						: 1'b0
+					: 1'b0
+				: 1'b0
+			: 1'b0;
+
+    assign mem_RFout2_in = ex_mem_xx_sw ? wb_RFwriteData : ex_RFout2;
+
     PipelineRegister exmem(
         .clk(clk), .rst(rst), .we(~mem_miss_stall), .flush(1'b0),
         .hlt_in(ex_hlt), .hlt_ou(mem_hlt),
@@ -146,10 +166,11 @@ module cpu(clk, rst_n, hlt, pc);
         .DataWE_in(ex_DataWe), .DataWE_ou(mem_DataWe),
         .inst_in(ex_inst), .inst_ou(mem_inst),
         .gppr1_in(ex_resultToPR), .gppr1_ou(mem_AluResult),
-        .gppr2_in(ex_RFout2), .gppr2_ou(mem_DataWriteDataFromPR),
+        .gppr2_in(mem_RFout2_in), .gppr2_ou(mem_DataWriteDataFromPR),
         .gppr3_in(ex_RFsrc2), .gppr3_ou(mem_DataWriteSrcReg)
     );
 
+
     // MEM stage
     assign mem_DataAddr = mem_AluResult;
     ForwardToMem forwardToMem(.memSrcSel(mem_MemMemForwarding), .memSrc(mem_DataWriteSrcReg), .wbDst(wb_RFdst), .willWrite(wb_RFwe));

diff --git a/testing/canonical-phase3/project-phase3-testbench.v b/testing/canonical-phase3/project-phase3-testbench.v
@@ -184,7 +184,7 @@ module cpu_ptb();
    assign WriteData = DUT.wb_RFwriteData;
    // If above is true, this should hold the Data being written to the register. (16 bits)
 
-   assign MemRead = DUT.MC.MAIN_MEMORY.enable;
+   assign MemRead = DUT.mem_inst[15:12]==4'b1000; //DUT.MC.MAIN_MEMORY.enable;
    // Is memory being read from, in this cycle. one bit signal (1 means yes, 0 means no)
 
    assign MemWrite = DUT.mem_DataWe;