Merge pull request eclipse-omr#3846 from dsouzai/tmQuery

Add Platform Agnostic TM Query

compiler/env/OMRCPU.hpp

@@ -131,6 +131,12 @@ class CPU
    bool isI386() { return _minorArch == TR::m_arch_i386; }
    bool isAMD64() { return _minorArch == TR::m_arch_amd64; }
 
+   /** @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
+    *
+    *  @return false; this is the default answer unless overridden by an extending class.
+    */
+   bool supportsTransactionalMemoryInstructions() { return false; }
+
 private:
    TR_Processor _processor;
 

compiler/p/env/OMRCPU.cpp

@@ -33,6 +33,12 @@ OMR::Power::CPU::getPPCis64bit()
    return (p >= TR_FirstPPC64BitProcessor)? true : false;
    }
 
+bool
+OMR::Power::CPU::supportsTransactionalMemoryInstructions()
+   {
+   return self()->getPPCSupportsTM();
+   }
+
 bool
 OMR::Power::CPU::isTargetWithinIFormBranchRange(intptrj_t targetAddress, intptrj_t sourceAddress)
    {

compiler/p/env/OMRCPU.hpp

@@ -65,6 +65,13 @@ class CPU : public OMR::CPU
    bool getPPCSupportsTM()  { return false; }
    bool getPPCSupportsLM()  { return false; }
 
+   /** @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
+    *         Alias of getPPCSupportsTM() as a platform agnostic query.
+    *
+    *  @return true if TM is available, false otherwise.
+    */
+   bool supportsTransactionalMemoryInstructions();
+
    /**
     * @brief Provides the maximum forward branch displacement in bytes reachable
     *        with an I-Form branch instruction.

compiler/x/env/OMRCPU.cpp

@@ -24,6 +24,7 @@
 #include "env/CPU.hpp"
 #include "env/JitConfig.hpp"
 #include "env/ProcessorInfo.hpp"
+#include "infra/Flags.hpp"
 #include "x/runtime/X86Runtime.hpp"
 
 
@@ -112,3 +113,10 @@ OMR::X86::CPU::testOSForSSESupport()
    {
    return false;
    }
+
+bool
+OMR::X86::CPU::supportsTransactionalMemoryInstructions()
+   {
+   flags32_t processorFeatureFlags8(self()->getX86ProcessorFeatureFlags8());
+   return processorFeatureFlags8.testAny(TR_RTM);
+   }

compiler/x/env/OMRCPU.hpp

@@ -64,6 +64,13 @@ class CPU : public OMR::CPU
 
    bool testOSForSSESupport();
 
+
+   /** @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
+    *
+    *  @return true if TM is available, false otherwise.
+    */
+   bool supportsTransactionalMemoryInstructions();
+
    /**
     * @brief Answers whether the distance between a target and source address
     *        is within the reachable RIP displacement range.

compiler/z/env/OMRCPU.cpp

@@ -27,7 +27,7 @@
 #pragma csect(STATIC,"OMRZCPUBase#S")
 #pragma csect(TEST,"OMRZCPUBase#T")
 
-#include "compiler/z/env/OMRCPU.hpp"
+#include "env/CPU.hpp"
 
 const char*
 OMR::Z::CPU::getProcessorName(int32_t machineId)
@@ -207,6 +207,12 @@ OMR::Z::CPU::getSupportsTransactionalMemoryFacility()
    return _flags.testAny(S390SupportsTM);
    }
 
+bool
+OMR::Z::CPU::supportsTransactionalMemoryInstructions()
+   {
+   return self()->getSupportsTransactionalMemoryFacility();
+   }
+
 
 bool
 OMR::Z::CPU::setSupportsTransactionalMemoryFacility(bool value)
@@ -375,4 +381,4 @@ OMR::Z::CPU::isTargetWithinBranchRelativeRILRange(intptrj_t targetAddress, intpt
    {
    return (targetAddress == sourceAddress + ((intptrj_t)((int32_t)((targetAddress - sourceAddress) / 2))) * 2) &&
             (targetAddress % 2 == 0);
-   }
+   }

compiler/z/env/OMRCPU.hpp

@@ -122,6 +122,12 @@ class CPU : public OMR::CPU
     *     Determines whether the Transactional Memory (TM) facility is available on the current processor.
     */
    bool getSupportsTransactionalMemoryFacility();
+
+   /** \brief
+    *     Determines whether the Transactional Memory (TM) facility is available on the current processor.
+    *     Alias of getSupportsTransactionalMemoryFacility() as a platform agnostic query.
+    */
+   bool supportsTransactionalMemoryInstructions();
 
    /** \brief
     *     Determines whether the Transactional Memory (TM) facility is available on the current processor.