[Kernel] Layernorm performance optimization

[mawong-amd]

This PR primarily creates optimized specializations of fused_add_rms_norm_kernel, used in many layernorms. It also includes a slightly optimized version of blockReduceSum/warpReduceSum which slightly reduce the number of shuffles done when the max block size is <=512 and known at compile time.

It is observed that fused_add_rms_norm is memory latency bound under many scenarios. The optimized implementation primarily derives its benefits by

1. Coalescing global memory transactions into larger operations, which reduces the number of stalls that need to be hidden. This is achieved by (implicitly) unrolling both of the for loops through the use of a vector struct.
2. Using a smaller block size when the number of blocks dispatched is large, which allows more blocks to simultaneously fit onto execution units and hence improves latency hiding.

The same ideas contained here can be applied to other relatively simple kernels which should be memory bound (e.g. some activation kernels).

More performance numbers can be provided as they become available or if requested. The existing test suite appears sufficient, but additional tests can be created on request.

Some examples of the speed up, as obtained by profiling via benchmark_latency on Llama2-70B (hidden size 8192), FP16, TP = 1, on MI300X:

• (input_len = output_len = batch_size = 128): Prefill improves to 305 ms from 440 ms.
• (input_len = 2048, output_len = 128, batch_size = 1): Prefill improves to 41 ms from 88 ms.
• For both cases above, decode improves to 7 ms from 11 ms.

Another optimization attempted was the use of shared memory, which effectively converts a global memory load into a shared memory load/store pair per item. While this improves performance when applied to baseline, it was not observed to improve performance on top of the current optimizations.

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[WoosukKwon]

@mawong-amd Thanks for submitting the PR! This optimization seems to be necessary for MI300x GPUs.

Unfortunately, I didn't see noticeable e2e performance boost for A100 GPUs. Is this expected? Also, I'm a bit worried about whether the new kernels keep the semantics of the current kernels. Could you double check?

[WoosukKwon]

Doesn't this change the semantics of the kernel since we do the addition in FP16/BF16 instead of FP32?

[mawong-amd]

It does in theory, however I've not noticed any observable effects from doing the addition in lower precision so far (even the logprobs of generated sequences are identical).

In terms of a possible increase in rounding error, this is likely still negligible compared to typical errors incurred during the reduction phase and in the approximate rsqrt.

The benefit of doing the addition in FP16/BF16 is that it can be implemented as a packed operation. But this step shouldn't be a bottleneck in any case.

[WoosukKwon]

I see, makes sense. Thanks for the explanation!

[WoosukKwon]

Can this affect other CUDA kernels?

[mawong-amd]

It could, but I haven't noticed any side effects and neither have the tests. The existing defines seem to originate from Torch's default defines as a legacy item and it's not clear to me if there's a good reason to retain them nowadays (e.g. seems like the recently added Punica extension similarly disables these defines).

If this is a concern, we could either limit the scope of removing these defines to this file or use free functions instead of operators (e.g. __hadd/__hadd2 for __half/__half2 operator+). But this increases code bloat and non-portability even further: the current implementation is already compromised to an extent by the (deficient) headers provided by CUDA/HIP (neither __hadd/__hadd2 as free functions or "heterogeneous" operators like float2::operator*(float) are consistently implemented in CUDA, while conversion operators/constructors are not consistently implemented by both).

[WoosukKwon]

Got it. Thanks for the explanation!

[mawong-amd]

@mawong-amd Thanks for submitting the PR! This optimization seems to be necessary for MI300x GPUs.

Unfortunately, I didn't see noticeable e2e performance boost for A100 GPUs. Is this expected? Also, I'm a bit worried about whether the new kernels keep the semantics of the current kernels. Could you double check?

Hi, I managed to run a few performance tests on H100 last night and also observed that there was no speed up. I looked at the PTX and SASS assembly and NVCC was not fusing the loads/stores as expected. It appears NVCC needs to know these global memory ops are aligned on a 16 byte boundary to unlock the full 128-bit coalesced op; I've added this alignment requirement to the vector struct and now I'm observing similar speedups on H100.

Preliminary numbers I'm seeing on H100 are:

• (input_len = output_len = batch_size = 128): Prefill improves to 92 ms from 178 ms.
• (input_len = 2048, output_len = 128, batch_size = 1): Prefill improves to 45 ms from 84 ms.
• For both cases above, decode improves to 3 ms from 8 ms.

One "drawback" of this change is we can now only enable optimizations when the hidden_size is a multiple of 8 and the tensor pointers are aligned on a 16 byte boundary. But these conditions should be met essentially all the time.

As for the changed semantics, I'll discuss it in the relevant review comment thread.

Thanks!

[mawong-amd]

Quick update on end-to-end runtime numbers. With the latest changes, I'm seeing small but observable improvements on H100.

Specifically, on the latency benchmark (50 iters on each test):

• (input_len = output_len = batch_size = 128): Improves to 11.463s from 11.658s. [1.7% improvement]
• (input_len = 2048, output_len = 128, batch_size = 1): Improves to 4.261s from 4.362s. [2.3% improvement]

[WoosukKwon]

@mawong-amd LGTM! Thanks for the optimization! Didn't know that RMSNorm can affect the performance this much.

[youkaichao]

I realized that this pr breaks cuda 11.8 support because of the usage of __half2 etc.

[mawong-amd]

I realized that this pr breaks cuda 11.8 support because of the usage of __half2 etc.

I think we can hotfix in a define guard to enable these optimizations only when the cuda version is > 11.8. Let me prepare a diff that does that.

[mawong-amd]

EDIT: Hotfix created as the following PR #3782

[youkaichao]

@mawong-amd Can you send a PR to land that patch?