bbb ve cape revisions

pdf files of the schematic are available in the bbb-hardware repo

cape & hw todo

• Add testpads on VE.Direct GND and VDD (next PCB rev.)
• Move Relay2 from P8.10 to P8.9
• Check this out

rev 0.62 schematic (released to production, only schematic: no PCB canges)

• Changed netlabel direction on toplevel schematic of VE.Direct_TX_1 from I/O to OUT. (cosmetic)
• Connect Relay_2 to TIMER_5 (P8.9) instead of TIMER_6 because timer_6 is not connected to the header on the BBE. This is done with a jumper on the header.
• To improve EMI behavior: Increase of R402 to 15R
• To improve 5V regulation: Increase of R404 to 100k

rev 0.61 (released to production, only schematic: no PCB changes)

Download the schematic & PCB PDF files

• Schematic corrected: L400 value 47µH, U204, D501, D502, D503, D514, D515 added rating

rev 0.6 (released to production)

• Added clear silk screen marking on the BeagleBone I/O headers (P100A, P100B)
• change names of BB expansion header pins to the same names as used in the bbb schematic
• Fix the bi-color LED, which was added in rev 4, messing up the boot configuration issue. Work around for rev 0.4 capes: remove R106 and R107. In rev 6 LED has been moved to GPIO1_17 and GPIO3_19.
• Fix high frequency audible noise coming from the power supply 47µH inductor will replace 18µH. Tested OK.
• Remove R225. It is not needed because of the pre-programmed bootloader.
• Renamed GND_MKIII to GND_MK3.
• D513 has incorrect pin/pad mapping in the library in V0.4. Corrected and verified.
• fix connections of digital inputs: three of them are shared with the eMMC and don't work. Corrected on PCB.
• Not done: Change 1 connection to allow intercheange of battery vs supercap. The battery has 0.8mm pins. If hole size is increased to 1mm to accommodate Supercap, the battery placement will be wobbly.
• Digital inputs (former S0) pinning (RJ12) changed to prevent short circuit to GND if a BMV shunt is accidentaly connected.
• change footprints of pluggable terminals (X400, X501, X502, X500, X300, X401) to auto-aligning versions. (1 hole offset) (Mechanical test PCB's ordered)
• PCBa coating must be included in assembly instruction
• change S0_CNT labels to DIG_INPUT and start numbering from 1, in schematic:
  • S0_CNT_0 -> DIG_INPUT_1
  • ...
  • S0_CNT_4 -> DIG_INPUT_5
• increase tank sensor series resistors to 10k to limit max current while Sitara chip is off or in reset (done)
• Increased creepage distance on Power net to 0.8mm under the connector where coating will be uneven. (Max. 70V)
• GND of CN500 moved to Pin 5. No infuence ont tester, because testpads remain unchanged.
• Verify ouput voltage of switch mode power supply
• Verify configuration settings of all IO (direction, pull up, pull down etc.) --> device tree setup made
• specify digital Input voltage ranges: 5V. Higher may work, depending on 3V3 current consumption on BBx.
• temperature test (bbe, full functional software, and in the final enclosure). The temperature rise is influenced by: power supply voltage, output current and ambient temperature. The hottest component Q400 stays at 105degC at 55V supply, 2.5A output and 40degC ambient.

rev 0.5 (No schematic changes):

• increase gap for the ethernet connector a little bit so that the three pin serial console behind it on the BBE remains accessible while cape is mounted.(done)
• increase track width of D401 reverse polarity protection from 0.5 to 0.8mm. It is sufficient now, but has little margin.(done) (This V0.5 board will never be produced, only a 2 layer mechanical sample has been made for mechanical fitment purposes)

rev 0.4 (schematic and pcb pdf)

Samples: 20 samples have been made. All patched to meet rev 0.6, except for the digital input connector. You'll see some patches on the capes for this connector, but they are not complete.

Changes:

• change ADC input circuits (no longer rely on internal uC diodes for the voltage clamping)
• change layout around Buck PSU (Q400 / D400 without thermal reliefs)
• change shape for LM5085 from VSSOP to MSOP (no change in PCB layout needed, only BOM)
• increase silkscreen printed revision to rev 4
• swap relay numbering: since X502A is on the right on the cape, label that RELAY_2, and label X502A as RELAY_1, in the schematic. (no change in PCB layout needed)
• change D504 and D510 to BAV99 (lower leakage) for improved temp. accuracy.
• remove unused labels from Sheet 1 : MK3_PWR, PROV_MK3_BRK, PROV_VE.BUS_PNL_DET, PWM_OUT_1, PWM_OUT_2
• updated top silk screen because of interferences
• move the AD connecto 4mm inward, decrease size of board to access sd card from outside box
• Make an S2 button on the cape to allow boot from SD.
• Move VE.BUS_STBY to GPIO 2_10 / P8.41 (To free the S2 pin)
• Add bi-color LED which will be used to show network connection state
• moved components of temperature inputs to make space for the bi color-LED
• add testpads
• updated top silk screen for improved readability

rev 0.3

samples have been made, but making them usable is quite some work

rev 0.2 (schematic and pcb pdf)

Ten protos were made, using preprogrammed mk3's that were thereafter keyloaded by jj. Except one, which has been sent to Sancloud. Few of the protos were altered to make the ADC input circuits work (see rev 4)

Changes:

• ??

Sample status

1/10
2/10
3/10
4/10
5/10
6/10 MVA desk- mk3 keyloaded - adc inputs modded - rtc replaced
7/10
8/10
9/10
10/10