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Cleanup
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@v-Golubev
v-Golubev committed Sep 15, 2023
1 parent ba77151 commit 1462a37
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Showing 7 changed files with 42 additions and 54 deletions.
34 changes: 15 additions & 19 deletions src/common/snippets/include/snippets/lowered/loop_manager.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@ class LinearIR::LoopManager {
// Returns dimension index if dimension indices for all entry and exit points are equal, and SIZE_MAX otherwise
size_t get_dim_idx() const;

// TODO: replace this temporary solution when ticket 119851 is implemented
using FirstIterHandler = std::function<bool(LinearIR&, LinearIR::constExprIt)>;
void set_first_iter_handler(FirstIterHandler handler);
FirstIterHandler fst_iter_handler = nullptr;
Expand Down Expand Up @@ -85,10 +86,12 @@ class LinearIR::LoopManager {
// Return Loop ID
template <typename T>
size_t mark_loop(LinearIR::constExprIt loop_begin_pos,
LinearIR::constExprIt loop_end_pos,
size_t work_amount, size_t work_amount_increment, size_t dim_idx,
const std::vector<T>& entries,
const std::vector<T>& exits) {
LinearIR::constExprIt loop_end_pos,
size_t work_amount,
size_t work_amount_increment,
size_t dim_idx,
const std::vector<T>& entries,
const std::vector<T>& exits) {
const auto loop_info = std::make_shared<LoopManager::LoopInfo>(work_amount, work_amount_increment, entries, exits);
for (auto& entry : loop_info->entry_points) {
entry.dim_idx = dim_idx;
Expand All @@ -105,10 +108,11 @@ class LinearIR::LoopManager {

template <typename T>
size_t mark_loop(LinearIR::constExprIt loop_begin_pos,
LinearIR::constExprIt loop_end_pos,
size_t work_amount, size_t increment,
const std::vector<T>& entries,
const std::vector<T>& exits) {
LinearIR::constExprIt loop_end_pos,
size_t work_amount,
size_t increment,
const std::vector<T>& entries,
const std::vector<T>& exits) {
const auto loop_info = std::make_shared<LoopManager::LoopInfo>(work_amount, increment, entries, exits);
const auto loop_id = this->add_loop_info(loop_info);
for (auto expr_it = loop_begin_pos; expr_it != loop_end_pos; ++expr_it) {
Expand All @@ -117,21 +121,13 @@ class LinearIR::LoopManager {
return loop_id;
}

template <typename T>
size_t mark_loop_with_old_loop_replacement(LinearIR::constExprIt loop_begin_pos,
LinearIR::constExprIt loop_end_pos,
size_t work_amount,
size_t increment,
const std::vector<T>& entries,
const std::vector<T>& exits,
const size_t old_id) {
const auto loop_info = std::make_shared<LoopManager::LoopInfo>(work_amount, increment, entries, exits);
const auto loop_id = this->add_loop_info(loop_info);
for (auto expr_it = loop_begin_pos; expr_it != loop_end_pos; ++expr_it) {
replace_loop_id(*expr_it, old_id, loop_id);
}
return loop_id;
}
const std::vector<LoopPort>& entries,
const std::vector<LoopPort>& exits,
const size_t old_id);

void fuse_loops(const LinearIR& linear_ir, size_t loop_id_upper, size_t loop_id_lower, bool fuse_into_upper = true);
void fuse_loops(LinearIR::constExprIt loop_begin_target, LinearIR::constExprIt loop_end_target,
Expand Down
15 changes: 15 additions & 0 deletions src/common/snippets/src/lowered/loop_manager.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -242,6 +242,21 @@ void LinearIR::LoopManager::mark_loop(LinearIR::constExprIt loop_begin_pos,
}
}

size_t LinearIR::LoopManager::mark_loop_with_old_loop_replacement(LinearIR::constExprIt loop_begin_pos,
LinearIR::constExprIt loop_end_pos,
size_t work_amount,
size_t increment,
const std::vector<LoopPort>& entries,
const std::vector<LoopPort>& exits,
const size_t old_id) {
const auto loop_info = std::make_shared<LoopManager::LoopInfo>(work_amount, increment, entries, exits);
const auto loop_id = this->add_loop_info(loop_info);
for (auto expr_it = loop_begin_pos; expr_it != loop_end_pos; ++expr_it) {
replace_loop_id(*expr_it, old_id, loop_id);
}
return loop_id;
}

void LinearIR::LoopManager::fuse_loops(const LinearIR& linear_ir, size_t loop_id_upper, size_t loop_id_lower, bool fuse_into_upper) {
LinearIR::constExprIt loop_begin_target, loop_end_target;
get_loop_bounds(linear_ir, fuse_into_upper ? loop_id_lower : loop_id_upper, loop_begin_target, loop_end_target);
Expand Down
3 changes: 1 addition & 2 deletions src/common/snippets/src/lowered/pass/validate_loops.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ bool ValidateLoops::run(LinearIR& linear_ir) {
for (size_t i = 0; i < loop_ids.size(); ++i) {
const auto id = loop_ids[i];
const auto dim_idx = loop_manager->get_loop_info(id)->get_dim_idx();
// if the loop has different dimension indexes, it don't have to meet the next requirements
if (dim_idx == SIZE_MAX)
continue;
if (std::find(dim_indexes.cbegin(), dim_indexes.cend(), dim_idx) != dim_indexes.cend()) {
Expand All @@ -64,8 +65,6 @@ bool ValidateLoops::run(LinearIR& linear_ir) {
OPENVINO_ASSERT(loop_manager->get_loop_info(loop_ids[i - 1])->outer_splited_loop,
"Incorrect Loop ID configuration: the outer Loop with splitted dimension should have `outer_splited_loop=True`");
}
OPENVINO_ASSERT(i == 0 || loop_manager->get_loop_info(loop_ids[i - 1])->get_dim_idx() >= dim_idx,
"Incorrect Loop ID configuration: dim_idx should be sorted in accordance with loop nesting");
dim_indexes.push_back(dim_idx);
}
validated_nested_loops.insert(loop_ids);
Expand Down
24 changes: 1 addition & 23 deletions src/plugins/intel_cpu/src/emitters/x64/jit_snippets_emitters.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -713,18 +713,12 @@ BrgemmEmitter::BrgemmEmitter(jit_generator* h, cpu_isa_t isa, const ExpressionPt
const auto& brgemm_node = as_type_ptr<ov::intel_cpu::BrgemmCPU>(expr->get_node());
if (brgemm_node->is_dynamic())
IE_THROW() << "Snippets don't support code generation for dynamic Brgemm";
const auto brgemm_copy = brgemm_node->is_with_data_repacking() ? brgemm_node->get_brgemm_copy() : nullptr;

std::vector<size_t> leading_dimensions;
std::vector<std::vector<size_t>> io_layouts;

auto init_scheduling_params = [&](const std::vector<size_t>& layout, const ov::Shape& io_shape) {
if (layout.empty()) {
// empty value indicates a planar layout
leading_dimensions.push_back(io_shape.back());
std::vector<size_t> default_layout(io_shape.size());
std::iota(default_layout.begin(), default_layout.end(), 0);
io_layouts.push_back(default_layout);
} else {
// The idea here is to find "2" (for 4D shapes) in the layout and multiply dimensions that are to the right
// This implies that "3" is the last layout value, otherwise this layout is not supported.
Expand All @@ -734,7 +728,6 @@ BrgemmEmitter::BrgemmEmitter(jit_generator* h, cpu_isa_t isa, const ExpressionPt
IE_THROW() << "BrgemmEmitter detected invalid layout values: check that this shape + layout combination is schedulable";
leading_dimensions.emplace_back(
std::accumulate(io_shape.end() - num_last_dims, io_shape.end(), 1, std::multiplies<size_t>()));
io_layouts.push_back(layout);
}
};

Expand All @@ -746,26 +739,11 @@ BrgemmEmitter::BrgemmEmitter(jit_generator* h, cpu_isa_t isa, const ExpressionPt
init_scheduling_params(input_1_desc->get_layout(), input_1_desc->get_shape());
init_scheduling_params(output_desc->get_layout(), output_desc->get_shape());

// We need find original M,N,K having layouts and ordered shapes
// Layout: 0, 1, 2, 3 => New layout: 0, 2, 1, 3
// Shape: 1, 3, 5, 9 => New Shape: 1, 5, 3, 9
// To find original 2nd dimension, we should find index of position value `2` in new layout
// and get dimension from new shape by this index
auto get_ordered_idx = [](const std::vector<size_t>& layout, size_t idx) {
return std::distance(layout.begin(), std::find(layout.begin(), layout.end(), idx));
};

const auto& output_subtensor = output_desc->get_subtensor();
const auto& input_0_subtensor = input_0_desc->get_subtensor();
m_K = *input_0_subtensor.rbegin();
m_M = *(output_subtensor.rbegin() + 1);
m_N = *output_subtensor.rbegin();
// TODO: N dim on input can be not equal to N dim on output. This case must be handled
if (brgemm_node->is_with_data_repacking()) {
const auto& C_shape = brgemm_node->get_output_shape(0);
const auto& C_layout = io_layouts[2];
m_N = C_shape[get_ordered_idx(C_layout, C_layout.size() - 1)];
}

auto brg0Prc = InferenceEngine::details::convertPrecision(brgemm_node->get_input_element_type(0));
auto brg1Prc = InferenceEngine::details::convertPrecision(brgemm_node->get_input_element_type(1));
Expand All @@ -783,7 +761,7 @@ BrgemmEmitter::BrgemmEmitter(jit_generator* h, cpu_isa_t isa, const ExpressionPt
m_brgCtx.N = m_N;
m_brgCtx.K = m_K;
m_brgCtx.LDA = leading_dimensions[0];
m_brgCtx.LDB = brgemm_node->is_with_data_repacking() ? rnd_up(m_N, brgemm_copy->get_n_block_size()) : leading_dimensions[1];
m_brgCtx.LDB = brgemm_node->is_with_data_repacking() ? rnd_up(m_N, brgemm_node->get_brgemm_copy()->get_n_block_size()) : leading_dimensions[1];
m_brgCtx.LDC = leading_dimensions[2];
m_brgCtx.dt_in0 = static_cast<dnnl_data_type_t>(DnnlExtensionUtils::IEPrecisionToDataType(brg0Prc));
m_brgCtx.dt_in1 = static_cast<dnnl_data_type_t>(DnnlExtensionUtils::IEPrecisionToDataType(brg1Prc));
Expand Down
2 changes: 0 additions & 2 deletions src/plugins/intel_cpu/src/transformations/snippets/x64/op/brgemm_cpu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -199,8 +199,6 @@ bool BrgemmCPU::visit_attributes(AttributeVisitor& visitor) {
visitor.on_attribute("blk_K", m_K_blk);
visitor.on_attribute("blk_N", m_N_blk);
visitor.on_attribute("beta", m_beta);
auto instance_id = get_instance_id();
visitor.on_attribute("instance_id", instance_id);
return true;
}

Expand Down
16 changes: 8 additions & 8 deletions src/plugins/intel_cpu/src/transformations/snippets/x64/pass/lowered/brgemm_blocking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -61,11 +61,11 @@ bool BrgemmBlocking::run(LinearIR& linear_ir) {
auto output_subtensor = output_desc->get_subtensor();

auto apply_m_blocking = [&]() {
const auto& input_shape_0 = input_0_desc->get_shape();
const auto& input_layout_0 = input_0_desc->get_layout();
const auto& output_shape = output_desc->get_shape();
const auto& output_layout = output_desc->get_layout();

const auto& m_idx = *(input_layout_0.rbegin() + 1);
const auto& m = input_shape_0[m_idx];
const auto& m_idx = *(output_layout.rbegin() + 1);
const auto& m = output_shape[m_idx];
const auto block_size_m = brgemm->get_m_block_size();
if (block_size_m >= m) {
*(input_0_subtensor.rbegin() + 1) = m;
Expand All @@ -83,11 +83,11 @@ bool BrgemmBlocking::run(LinearIR& linear_ir) {
};

auto apply_n_blocking = [&]() {
const auto& input_shape_1 = input_1_desc->get_shape();
const auto& input_layout_1 = input_1_desc->get_layout();
const auto& output_shape = output_desc->get_shape();
const auto& output_layout = output_desc->get_layout();

const auto& n_idx = *input_layout_1.rbegin();
const auto& n = input_shape_1[n_idx];
const auto& n_idx = *output_layout.rbegin();
const auto& n = output_shape[n_idx];
const auto block_size_n = brgemm->get_n_block_size();
if (block_size_n >= n) {
*input_1_subtensor.rbegin() = n;
Expand Down
2 changes: 2 additions & 0 deletions ...lugins/intel_cpu/src/transformations/snippets/x64/pass/set_brgemm_cpu_blocking_params.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,8 @@ pass::SetBrgemmCPUBlockingParams::SetBrgemmCPUBlockingParams() {
if (brgemm->is_with_data_repacking()) {
const auto brgemm_copy_b = brgemm->get_brgemm_copy();
const auto out_dims = snippets::utils::get_planar_pshape(brgemm_copy_b->output(0)).get_shape();
// Due to the semantic of BrgemmCopyB operation its N dimension might be not equal
// to the corresponding BrgemmCPU dimension.
const auto N = *out_dims.rbegin();

const bool isAMXSupported = dnnl::impl::cpu::x64::mayiuse(dnnl::impl::cpu::x64::avx512_core_amx);
Expand Down

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