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RASI Generator #1171

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merged 86 commits into from
Apr 7, 2024
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860e66c
Started work on RASI generator
PBHTasche Feb 1, 2024
97e4ad3
Solidified architecture of RASI generator
PBHTasche Feb 1, 2024
c441e63
Refined execution state tracking
PBHTasche Feb 1, 2024
df1654b
Working on Control Flow Graph for VerCors
PBHTasche Feb 8, 2024
258827c
Added indexing system for nested statements
PBHTasche Feb 8, 2024
e1cf533
Added context indices for subroutine calls
PBHTasche Feb 9, 2024
9e766d0
Continued working on indexing system
PBHTasche Feb 12, 2024
023ebe3
Fixed typo
PBHTasche Feb 12, 2024
485a276
Allowed sets of successor indices, added support for fork, added recu…
PBHTasche Feb 12, 2024
967a6c4
Added support for break, continue, return and throw and started on sw…
PBHTasche Feb 13, 2024
d36e867
Added general support for statements hidden in expressions with side …
PBHTasche Feb 13, 2024
7aedcd4
Improved support for expressions with side effects
PBHTasche Feb 13, 2024
344df78
Continued support for expression side effects, some syntax fixes, add…
PBHTasche Feb 14, 2024
c4a7755
Syntax fixes, project compiles
PBHTasche Feb 14, 2024
4bbb2ab
Implemented GraphViz/DOT printer for control flow graph
PBHTasche Feb 14, 2024
c89a728
Started work on frontend support for CFG conversion
PBHTasche Feb 14, 2024
1f994f6
Fixed implementation of subroutine invocations
PBHTasche Feb 14, 2024
f9672e0
Renamed VeSUV pass to avoid confusion
PBHTasche Feb 15, 2024
77e242a
Connected frontend to backend for control flow graph printer
PBHTasche Feb 15, 2024
817d067
Fixed small errors preventing execution
PBHTasche Feb 15, 2024
dc5d57b
Fixed an infinite recursion when referring back to incompletely trans…
PBHTasche Feb 15, 2024
b7c114e
Added path conditions to CFG edges
PBHTasche Feb 15, 2024
7daac9e
Finding main method automatically, added support for unresolved-conta…
PBHTasche Feb 15, 2024
2bc3a50
Changed fork to create new stack; enabled terminal CFG nodes
PBHTasche Feb 16, 2024
585c3c7
Enable terminal node
PBHTasche Feb 16, 2024
8da6793
Added support for edge conditions in expression side effects
PBHTasche Feb 16, 2024
bd091dc
Started work on CFG traversal for RASI generation
PBHTasche Feb 16, 2024
d43a762
Working on RASI generator
PBHTasche Feb 16, 2024
0d22af4
Added uncertain values to RASI generator
PBHTasche Feb 19, 2024
8f212d1
Finished expression side effects for With and Then
PBHTasche Feb 19, 2024
e2e5cf0
Started with uncertainty arithmetic; made compilable
PBHTasche Feb 19, 2024
e789ad9
Made options for index switches more explicit
PBHTasche Feb 19, 2024
465798c
Syntax fixes
PBHTasche Feb 19, 2024
8212df8
Added expression evaluations to lock and process related statements
PBHTasche Feb 20, 2024
39cb088
Implemented some logic for interval arithmetic, started on implementa…
PBHTasche Feb 20, 2024
88dcc40
Started implementing switch statements for CFG
PBHTasche Feb 20, 2024
33ac279
Made variable valuations abstract in RASI generator
PBHTasche Feb 20, 2024
a23673b
Implemented some abstract process logic; added edges to RASI; improve…
PBHTasche Feb 21, 2024
c215e4e
Added option to compare booleans in expressions
PBHTasche Feb 21, 2024
c02cb24
Added a printer for the RASI state space, but not connected to the fr…
PBHTasche Feb 21, 2024
cff50d2
Improved support for uncertain integer values
PBHTasche Feb 21, 2024
deb912f
Added infrastructure for decoding assumption-induced state changes
PBHTasche Feb 21, 2024
a97665b
Implemented extraction of state changes out of assumptions and postco…
PBHTasche Feb 22, 2024
d9a5b85
Started work on connecting the RASI generator to the frontend (doesn'…
PBHTasche Feb 22, 2024
8235eff
Added comments to VeSUV command line options
PBHTasche Feb 23, 2024
b64bf51
Fixed type error, project compiles
PBHTasche Feb 23, 2024
7544658
Progress on switch/case implementation
PBHTasche Feb 23, 2024
40d7059
Fixing the most severe bugs, program compiles and runs
PBHTasche Feb 23, 2024
e445aa2
Refactored CFG generation to use statement supertypes instead of patt…
PBHTasche Feb 26, 2024
fd3739b
Removed expression container node before resolution of expression
PBHTasche Feb 26, 2024
53709b3
Fixed return followed by branches; removed scope nodes from CFG
PBHTasche Feb 26, 2024
7c3857c
Added node back to CFG if it is the first context of a run method; re…
PBHTasche Feb 27, 2024
9b1c7bc
Added new keyword 'vesuv_entry' for main method
PBHTasche Mar 5, 2024
7607112
Made MainMethod global rather than class declaration
PBHTasche Mar 5, 2024
838b12c
Working on effect of collection updates on collection entries
PBHTasche Mar 5, 2024
c4728bd
[FAILED] Tried to switch from sequences to individual variables
PBHTasche Mar 11, 2024
fd8f40e
Revert "[FAILED] Tried to switch from sequences to individual variables"
PBHTasche Mar 11, 2024
7bda0ad
Implemented sequence semantics under uncertainty
PBHTasche Mar 12, 2024
693064b
Some documentation for the abstract state
PBHTasche Mar 12, 2024
1aefbaa
Improved support for extracting information out of assumptions
PBHTasche Mar 13, 2024
978f078
Removed impossible states from assumption resolution
PBHTasche Mar 13, 2024
c7136dd
Fixed errors in the VeSUV implementation
PBHTasche Mar 14, 2024
a9f08ab
Fixed some errors in the CFG and variable resolution for the RASI
PBHTasche Mar 14, 2024
8854b98
Added support for semantics of more expressions
PBHTasche Mar 14, 2024
f233552
Fixed some errors in VeSUV from porting to VerCors 2.0.0
PBHTasche Mar 14, 2024
9c83f67
Fixed an error where state class constructors would ensure idle tokens
PBHTasche Mar 15, 2024
ce9bd80
Implemented return value resolution from contracts; cleaned up constr…
PBHTasche Mar 15, 2024
2280f94
Fixed some type errors
PBHTasche Mar 15, 2024
8b56687
Fixed an error in the redundant state filter of the RASI generator
PBHTasche Mar 18, 2024
1e109ff
Implemented verification support for vesuv main method
PBHTasche Mar 18, 2024
1299e5b
Enabled parsing and resolution of VeSUV main method
PBHTasche Mar 18, 2024
6123a98
Started implementing support for considering atomic blocks
PBHTasche Mar 18, 2024
4671b54
Added predicate unfolding in search of global invariant
PBHTasche Mar 18, 2024
b9bca0b
Added explicit checks for loop and method contracts into the AST
PBHTasche Mar 19, 2024
8640b79
Fixed an error where atomic blocks would never terminate if they coul…
PBHTasche Mar 19, 2024
35035f2
Documentation; Fixed an error where atomic steps would always step ov…
PBHTasche Mar 20, 2024
99747d1
Cleanup
PBHTasche Mar 20, 2024
dbeca4e
Tried to change constraint solving implementation
PBHTasche Mar 20, 2024
82854f7
Revert "Tried to change constraint solving implementation"
PBHTasche Mar 20, 2024
f10d417
Taking into account expression viability for constraint resolution; a…
PBHTasche Mar 20, 2024
960ed51
Fixed an error where global invariant assertions were not properly de…
PBHTasche Mar 20, 2024
eba3309
Changed encoding of find_minimum_advance in VeSUV to avoid sequence p…
PBHTasche Mar 21, 2024
c6db2ae
Added mechanism by which variables in function contracts are uncertai…
PBHTasche Mar 21, 2024
14cd710
Fixed errors in uncertain value comparisons; removed initial state fr…
PBHTasche Mar 21, 2024
6933480
Fixed errors with sequence operations and object comparison; added de…
PBHTasche Mar 22, 2024
1d6b44a
Merge branch 'dev' into rasi_generator
pieter-bos Apr 7, 2024
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3 changes: 2 additions & 1 deletion build.sc
Original file line number Diff line number Diff line change
Expand Up @@ -402,7 +402,8 @@ object vercors extends Module {
)
}
def deps = Agg(
ivy"org.antlr:antlr4-runtime:4.8"
ivy"org.antlr:antlr4-runtime:4.8",
ivy"org.apache.logging.log4j:log4j-to-slf4j:2.23.1",
)
override def moduleDeps = Seq(hre, col, serialize)
override def bareResourcePaths = T { Seq(vcllvm.compile().path / os.up) }
Expand Down
143 changes: 74 additions & 69 deletions src/col/vct/col/ast/Node.scala

Large diffs are not rendered by default.

Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,6 @@ trait InstancePredicateImpl[G] extends ClassDeclarationImpl[G] with AbstractPred

override def layout(implicit ctx: Ctx): Doc = Group(
Doc.rspread(layoutModifiers) <> "resource" <+> ctx.name(this) <> "(" <> Doc.args(args) <> ")" <>
body.map(Text(" =") <>> _).getOrElse(Text(";"))
body.map(Text(" =") <>> _ <> ";").getOrElse(Text(";"))
)
}
12 changes: 12 additions & 0 deletions src/col/vct/col/ast/declaration/cls/VeSUVMainMethodImpl.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
package vct.col.ast.declaration.cls

import vct.col.ast.VeSUVMainMethod
import vct.col.print.{Ctx, Doc, Empty, Text}
import vct.col.ast.ops.VeSUVMainMethodOps

trait VeSUVMainMethodImpl[G] extends VeSUVMainMethodOps[G] { this: VeSUVMainMethod[G] =>
override def layout(implicit ctx: Ctx): Doc =
Doc.stack(Seq(
Text("vesuv_entry") <> body.map(Empty <+> _.layoutAsBlock).getOrElse(Text(";")),
))
}
2 changes: 1 addition & 1 deletion src/col/vct/col/ast/declaration/global/ClassImpl.scala
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ trait ClassImpl[G] extends Declarator[G] with ClassOps[G] { this: Class[G] =>
def transSupportArrows: Seq[(Class[G], Class[G])] = transSupportArrows(Set.empty)

def layoutLockInvariant(implicit ctx: Ctx): Doc =
Text("lock_invariant") <+> intrinsicLockInvariant <+/> Empty
Text("lock_invariant") <+> intrinsicLockInvariant <> ";" <+/> Empty

override def layout(implicit ctx: Ctx): Doc =
(if(intrinsicLockInvariant == tt[G]) Empty else Doc.spec(Show.lazily(layoutLockInvariant(_)))) <>
Expand Down
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/lang/silver/SilverFieldAssignImpl.scala
Original file line number Diff line number Diff line change
@@ -1,10 +1,12 @@
package vct.col.ast.lang.silver

import vct.col.ast.SilverFieldAssign
import vct.col.ast.{Expr, SilverFieldAssign}
import vct.col.print.{Ctx, Doc, Precedence, Text}
import vct.col.ast.ops.SilverFieldAssignOps

trait SilverFieldAssignImpl[G] extends SilverFieldAssignOps[G] { this: SilverFieldAssign[G] =>
override def layout(implicit ctx: Ctx): Doc =
obj.bind(Precedence.POSTFIX) <> "." <> ctx.name(field) <+> ":=" <+> value

override def expr: Expr[G] = this.value
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/lang/silver/SilverLocalAssignImpl.scala
Original file line number Diff line number Diff line change
@@ -1,10 +1,12 @@
package vct.col.ast.lang.silver

import vct.col.ast.SilverLocalAssign
import vct.col.ast.{Expr, SilverLocalAssign}
import vct.col.print.{Ctx, Doc, Text}
import vct.col.ast.ops.SilverLocalAssignOps

trait SilverLocalAssignImpl[G] extends SilverLocalAssignOps[G] { this: SilverLocalAssign[G] =>
override def layout(implicit ctx: Ctx): Doc =
Text(ctx.name(v)) <+> ":=" <+> value

override def expr: Expr[G] = this.value
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
package vct.col.ast.statement.behavior

import vct.col.ast.{Expr, ExpressionContainerStatement}
import vct.col.ast.statement.StatementImpl

trait ExpressionContainerStatementImpl[G] extends StatementImpl[G] { this: ExpressionContainerStatement[G] =>
def expr: Expr[G]
}
2 changes: 2 additions & 0 deletions src/col/vct/col/ast/statement/exceptional/ReturnImpl.scala
Original file line number Diff line number Diff line change
Expand Up @@ -18,4 +18,6 @@ trait ReturnImpl[G] extends ExceptionalStatementImpl[G] with ReturnOps[G] { this

override def layout(implicit ctx: Ctx): Doc =
Text("return") <> (if(result == Void[G]()) Text(";") else Empty <+> result <> ";")

override def expr: Expr[G] = this.result
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/exceptional/ThrowImpl.scala
Original file line number Diff line number Diff line change
@@ -1,10 +1,12 @@
package vct.col.ast.statement.exceptional

import vct.col.ast.Throw
import vct.col.ast.{Expr, Throw}
import vct.col.print.{Ctx, Doc, Text}
import vct.col.ast.ops.ThrowOps

trait ThrowImpl[G] extends ThrowOps[G] { this: Throw[G] =>
override def layout(implicit ctx: Ctx): Doc =
Text("throw") <+> obj <> ";"

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/AssertImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Assert
import vct.col.ast.{Assert, Expr}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.AssertOps

Expand All @@ -15,4 +15,6 @@ trait AssertImpl[G] extends AssertOps[G] { this: Assert[G] =>
case Ctx.Silver => layoutSilver
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.res
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/AssumeImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Assume
import vct.col.ast.{Assume, Expr}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.AssumeOps

Expand All @@ -15,4 +15,6 @@ trait AssumeImpl[G] extends AssumeOps[G] { this: Assume[G] =>
case Ctx.Silver => layoutSilver
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.assn
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/CommitImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Commit
import vct.col.ast.{Commit, Expr}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.CommitOps

Expand All @@ -9,4 +9,6 @@ trait CommitImpl[G] extends CommitOps[G] { this: Commit[G] =>
Text("commit") <+> obj <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/ExhaleImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Exhale
import vct.col.ast.{Exhale, Expr}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.ExhaleOps

Expand All @@ -15,4 +15,6 @@ trait ExhaleImpl[G] extends ExhaleOps[G] { this: Exhale[G] =>
case Ctx.Silver => layoutSilver
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.res
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/FoldImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Fold
import vct.col.ast.{Expr, Fold}
import vct.col.ast.node.NodeFamilyImpl
import vct.col.ast.util.CheckFoldUnfoldTarget
import vct.col.print.{Ctx, Doc, Show, Text}
Expand All @@ -17,4 +17,6 @@ trait FoldImpl[G] extends NodeFamilyImpl[G] with CheckFoldUnfoldTarget[G] with F
case Ctx.Silver => layoutSilver
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.res
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/ForkImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Fork
import vct.col.ast.{Expr, Fork}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.ForkOps

Expand All @@ -9,4 +9,6 @@ trait ForkImpl[G] extends ForkOps[G] { this: Fork[G] =>
Text("fork") <+> obj <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/HavocImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Havoc
import vct.col.ast.{Expr, Havoc}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.HavocOps

Expand All @@ -9,4 +9,6 @@ trait HavocImpl[G] extends HavocOps[G] { this: Havoc[G] =>
Text("havoc") <+> loc <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.loc
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/InhaleImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Inhale
import vct.col.ast.{Expr, Inhale}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.InhaleOps

Expand All @@ -15,4 +15,6 @@ trait InhaleImpl[G] extends InhaleOps[G] { this: Inhale[G] =>
case Ctx.Silver => layoutSilver
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.res
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/JoinImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Join
import vct.col.ast.{Expr, Join}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.JoinOps

Expand All @@ -9,4 +9,6 @@ trait JoinImpl[G] extends JoinOps[G] { this: Join[G] =>
Text("join") <+> obj <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/LockImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Lock
import vct.col.ast.{Expr, Lock}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.LockOps

Expand All @@ -9,4 +9,6 @@ trait LockImpl[G] extends LockOps[G] { this: Lock[G] =>
Text("lock") <+> obj <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/NotifyImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Notify
import vct.col.ast.{Expr, Notify}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.NotifyOps

Expand All @@ -9,4 +9,6 @@ trait NotifyImpl[G] extends NotifyOps[G] { this: Notify[G] =>
Text("notify") <+> obj <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/RefuteImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Refute
import vct.col.ast.{Expr, Refute}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.RefuteOps

Expand All @@ -15,4 +15,6 @@ trait RefuteImpl[G] extends RefuteOps[G] { this: Refute[G] =>
case Ctx.Silver => layoutSilver
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.assn
}
6 changes: 4 additions & 2 deletions src/col/vct/col/ast/statement/terminal/SendImpl.scala
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Send
import vct.col.print.{Ctx, Doc, Show, Text, Group}
import vct.col.ast.{Expr, Send}
import vct.col.print.{Ctx, Doc, Group, Show, Text}
import vct.col.ast.ops.SendOps

trait SendImpl[G] extends SendOps[G] { this: Send[G] =>
Expand All @@ -10,4 +10,6 @@ trait SendImpl[G] extends SendOps[G] { this: Send[G] =>

override def layout(implicit ctx: Ctx): Doc =
Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.res
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/UnfoldImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Unfold
import vct.col.ast.{Expr, Unfold}
import vct.col.ast.node.NodeFamilyImpl
import vct.col.ast.util.CheckFoldUnfoldTarget
import vct.col.print.{Ctx, Doc, Show, Text}
Expand All @@ -17,4 +17,6 @@ trait UnfoldImpl[G] extends NodeFamilyImpl[G] with CheckFoldUnfoldTarget[G] with
case Ctx.Silver => layoutSilver
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.res
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/UnlockImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Unlock
import vct.col.ast.{Expr, Unlock}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.UnlockOps

Expand All @@ -9,4 +9,6 @@ trait UnlockImpl[G] extends UnlockOps[G] { this: Unlock[G] =>
Text("unlock") <+> obj <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/WaitImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.Wait
import vct.col.ast.{Expr, Wait}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.WaitOps

Expand All @@ -9,4 +9,6 @@ trait WaitImpl[G] extends WaitOps[G] { this: Wait[G] =>
Text("wait") <+> obj <> ";"

override def layout(implicit ctx: Ctx): Doc = Doc.inlineSpec(Show.lazily(layoutSpec(_)))

override def expr: Expr[G] = this.obj
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/terminal/WandApplyImpl.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
package vct.col.ast.statement.terminal

import vct.col.ast.WandApply
import vct.col.ast.{Expr, WandApply}
import vct.col.print.{Ctx, Doc, Show, Text}
import vct.col.ast.ops.WandApplyOps

Expand All @@ -12,4 +12,6 @@ trait WandApplyImpl[G] extends WandApplyOps[G] { this: WandApply[G] =>
case Ctx.Silver => Text("apply") <+> res
case _ => Doc.inlineSpec(Show.lazily(layoutSpec(_)))
}

override def expr: Expr[G] = this.res
}
4 changes: 3 additions & 1 deletion src/col/vct/col/ast/statement/veymont/PVLSeqAssignImpl.scala
Original file line number Diff line number Diff line change
@@ -1,10 +1,12 @@
package vct.col.ast.statement.veymont

import vct.col.ast.PVLSeqAssign
import vct.col.ast.{Expr, PVLSeqAssign}
import vct.col.print.{Ctx, Doc, Group, Text}
import vct.col.ast.ops.PVLSeqAssignOps

trait PVLSeqAssignImpl[G] extends PVLSeqAssignOps[G] { this: PVLSeqAssign[G] =>
override def layout(implicit ctx: Ctx): Doc =
Group(Text(receiver.decl.name) <> "." <> ctx.name(field) <+> ":=" <+> value.show)

override def expr: Expr[G] = this.value
}
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