define CACHE_LINE_SIZE in arch_*.h

Signed-off-by: Mathieu Desnoyers <[email protected]>
urcu · Sep 29, 2009 · b4e52e3 · b4e52e3
1 parent 49d7d15
commit b4e52e3
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Showing 16 changed files with 8 additions and 39 deletions.
diff --git a/tests/api_ppc.h b/tests/api_ppc.h
@@ -73,7 +73,7 @@
 
 #define CONFIG_PPC64
 
-#define CACHE_LINE_SIZE 128
+/*#define CACHE_LINE_SIZE 128 */
 #define ____cacheline_internodealigned_in_smp \
 	__attribute__((__aligned__(1 << 7)))
 
@@ -665,7 +665,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
  */
 
 #ifndef CACHE_LINE_SIZE
-#define CACHE_LINE_SIZE 128
+/* #define CACHE_LINE_SIZE 128 */
 #endif /* #ifndef CACHE_LINE_SIZE */
 
 /*

diff --git a/tests/api_x86.h b/tests/api_x86.h
@@ -71,7 +71,7 @@
  * Machine parameters.
  */
 
-#define CACHE_LINE_SIZE 64
+/* #define CACHE_LINE_SIZE 64 */
 #define ____cacheline_internodealigned_in_smp \
 	__attribute__((__aligned__(1 << 6)))
 

diff --git a/tests/test_mutex.c b/tests/test_mutex.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_perthreadlock.c b/tests/test_perthreadlock.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_perthreadlock_timing.c b/tests/test_perthreadlock_timing.c
@@ -34,9 +34,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/tests/test_qsbr.c b/tests/test_qsbr.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_qsbr_gc.c b/tests/test_qsbr_gc.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_qsbr_timing.c b/tests/test_qsbr_timing.c
@@ -32,9 +32,6 @@
 #include <sys/syscall.h>
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/tests/test_rwlock.c b/tests/test_rwlock.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_rwlock_timing.c b/tests/test_rwlock_timing.c
@@ -33,9 +33,6 @@
 #include <pthread.h>
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/tests/test_urcu.c b/tests/test_urcu.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_urcu_defer.c b/tests/test_urcu_defer.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_urcu_gc.c b/tests/test_urcu_gc.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_urcu_timing.c b/tests/test_urcu_timing.c
@@ -32,9 +32,6 @@
 #include <sys/syscall.h>
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
@@ -28,6 +28,9 @@
 #define CONFIG_HAVE_FENCE 1
 #define CONFIG_HAVE_MEM_COHERENCY
 
+/* Include size of POWER5+ L3 cache lines: 256 bytes */
+#define CACHE_LINE_SIZE	256
+
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
 #endif

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
@@ -29,6 +29,8 @@
 #define CONFIG_HAVE_FENCE 1
 #define CONFIG_HAVE_MEM_COHERENCY
 
+#define CACHE_LINE_SIZE	128
+
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
 #endif