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Factor out recipes for building SW RTL simulators into Makefrags
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,40 @@ | ||
| # VCS RTL Simulation Makefrag | ||
| # | ||
| # This makefrag stores common recipes for building RTL simulators with VCS | ||
| # | ||
| # Compulsory variables: | ||
| # All those described Makefrag-verilator | ||
| # vcs_wrapper_v: An additional verilog wrapper around the DUT not used in verilator | ||
| # CLOCK_PERIOD: Self explanatory | ||
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| VCS ?= vcs -full64 | ||
| override VCS_FLAGS := -quiet -timescale=1ns/1ps +v2k +rad +vcs+initreg+random +vcs+lic+wait \ | ||
| -notice -line +lint=all,noVCDE,noONGS,noUI -quiet -debug_pp +no_notifier -e vcs_main -cpp $(CXX) \ | ||
| -CFLAGS "$(CXXFLAGS) -DVCS -I$(VCS_HOME)/include" \ | ||
| -LDFLAGS "$(LDFLAGS) -lmidas" \ | ||
| +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ | ||
| +define+RANDOMIZE_MEM_INIT \ | ||
| +define+RANDOMIZE_REG_INIT \ | ||
| +define+RANDOMIZE_GARBAGE_ASSIGN \ | ||
| +define+RANDOMIZE_INVALID_ASSIGN \ | ||
| $(VCS_FLAGS) | ||
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| vcs_v := $(vcs_wrapper_v) $(emul_v) | ||
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| $(OUT_DIR)/$(DESIGN): $(emul_h_inc) $(vcs_v) $(emul_cc) $(emul_h) | ||
| mkdir -p $(OUT_DIR) | ||
| rm -rf $(GEN_DIR)/$(DESIGN).csrc | ||
| rm -rf $(OUT_DIR)/$(DESIGN).daidir | ||
| $(VCS) $(VCS_FLAGS) -Mdir=$(GEN_DIR)/$(DESIGN).csrc +vc+list \ | ||
| +define+STOP_COND=!emul.reset +define+PRINTF_COND=!emul.reset \ | ||
| -CFLAGS "-include $<" \ | ||
| -o $@ $(GEN_DIR)/$(DESIGN)-const.vh $(vcs_v) $(emul_cc) | ||
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| $(OUT_DIR)/$(DESIGN)-debug: $(emul_h_inc) $(vcs_v) $(emul_cc) $(emul_h) | ||
| mkdir -p $(OUT_DIR) | ||
| rm -rf $(GEN_DIR)/$(DESIGN)-debug.csrc | ||
| rm -rf $(OUT_DIR)/$(DESIGN)-debug.daidir | ||
| $(VCS) $(VCS_FLAGS) -Mdir=$(GEN_DIR)/$(DESIGN)-debug.csrc +vc+list \ | ||
| +define+STOP_COND=!emul.reset +define+PRINTF_COND=!emul.reset +define+DEBUG \ | ||
| -CFLAGS "-include $<" \ | ||
| -o $@ $(GEN_DIR)/$(DESIGN)-const.vh $(vcs_v) $(emul_cc) |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,36 @@ | ||
| # Verilator RTL Simulation Makefrag | ||
| # | ||
| # This makefrag stores common recipes for building RTL simulators with Verilator | ||
| # | ||
| # Compulsory variables: | ||
| # OUT_DIR: See Makefile | ||
| # GEN_DIR: See Makefile | ||
| # DESIGN: See Makefile | ||
| # emul_h_inc: A c header with macro definitions to be included in all compilation units | ||
| # emul_cc: C++ sources | ||
| # emul_h: C++ headers | ||
| # emul_v: verilog sources | ||
| # | ||
| # Verilator Only: | ||
| # top_module: The top of the DUT | ||
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| VERILATOR ?= verilator --cc --exe | ||
| override VERILATOR_FLAGS := --assert -Wno-STMTDLY -O3 \ | ||
| -CFLAGS "$(CXXFLAGS)" -LDFLAGS "$(LDFLAGS) -lmidas" \ | ||
| $(VERILATOR_FLAGS) | ||
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| $(OUT_DIR)/V$(DESIGN): $(emul_h_inc) $(emul_v) $(emul_cc) $(emul_h) | ||
| mkdir -p $(OUT_DIR) | ||
| rm -rf $(GEN_DIR)/V$(DESIGN).csrc | ||
| $(VERILATOR) $(VERILATOR_FLAGS) --top-module $(top_module) -Mdir $(GEN_DIR)/V$(DESIGN).csrc \ | ||
| -CFLAGS "-include $< -include $(GEN_DIR)/V$(DESIGN).csrc/V$(top_module).h" \ | ||
| -o $@ $(emul_v) $(DRIVER) $(emul_cc) $(endpoint_cc) | ||
| $(MAKE) -C $(GEN_DIR)/V$(DESIGN).csrc -f V$(top_module).mk | ||
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| $(OUT_DIR)/V$(DESIGN)-debug: $(emul_h_inc) $(emul_v) $(emul_cc) $(emul_h) | ||
| mkdir -p $(OUT_DIR) | ||
| rm -rf $(GEN_DIR)/V$(DESIGN)-debug.csrc | ||
| $(VERILATOR) $(VERILATOR_FLAGS) --trace --top-module $(top_module) -Mdir $(GEN_DIR)/V$(DESIGN)-debug.csrc \ | ||
| -CFLAGS "-include $< -include $(GEN_DIR)/V$(DESIGN)-debug.csrc/V$(top_module).h" \ | ||
| -o $@ $(emul_v) $(emul_cc) | ||
| $(MAKE) -C $(GEN_DIR)/V$(DESIGN)-debug.csrc -f V$(top_module).mk |