Merge pull request #756 from ucb-bar/16-largeboom

Add 16-core LargeBOOM config to firechip
ucb-bar · Jan 13, 2021 · f7a98f2 · f7a98f2
2 parents e9f64a8 + c481dc2
commit f7a98f2
Showing 1 changed file with 11 additions and 0 deletions.
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -204,3 +204,14 @@ class FireSimMulticlockRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
   new FireSimRocketConfig)
 
+//**********************************************************************************
+// System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations
+// - Requires MTModels and MCRams mixins as prefixes to the platform config
+// - May require larger build instances or JVM memory footprints
+//*********************************************************************************/
+class FireSim16LargeBoomConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new boom.common.WithNLargeBooms(16) ++
+  new chipyard.config.AbstractConfig)