A soft RISC processor on Xilinx FPGA with Verilog and an assembler with Python. It is my undergrad graduation project in Istanbul Technical University.
Processor is designed on Xilinx ISE 13.2 with Verilog. Processor tested on Xilinx ATLYS board.
Also processor simulated in Logisim logic simulation program. Logisim simulation circuits are in logisim_processor folder.
Assembler for new instruction set is developed with Python 2. Python assembler is in python_assembler folder.
Detailed information, usage and examples about project can be found in Project report.
For detailed information: Project report
For brief information: Project presentation