aarch64: Add DSB instruction Armv8.7-a variant

This patch adds new variant (nXS) of DSB memory barrier instruction
available in Armv8.7-a. New nXS variant has different encoding in
comparison with pre Armv8.7-a DSB memory barrier variant thus new
instruction and new operand was added.

DSB memory nXS barrier variant specifies the limitation on the barrier
operation. Allowed values are:

	DSB SYnXS|#28
	DSB ISHnXS|#24
	DSB NSHnXS|#20
	DSB OSHnXS|#16

Please note that till now,  for barriers, barrier operation was encoded in
4-bit unsigned immediate CRm field (in the range 0 to 15).
For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned
assembly instruction immediate, encoded in instruction in two bits CRm<3:2>:

		CRm<3:2>  #imm
		  00       16
		  01       20
		  10       24
		  11       28

This patch extends current AArch64 barrier instructions with above mapping.

Notable patch changes include:
+ New DSB memory barrier variant encoding for Armv8.7-a.
+ New operand BARRIER_DSB_NXS for above instruction in order to
distinguish between existing and new DSB instruction flavour.
+ New set of DSB nXS barrier options.
+ New instruction inserter and extractor map between instruction
immediate 5-bit value and 2-bit CRm field of the instruction itself (see
FLD_CRm_dsb_nxs).
+ Regeneration of aarch64-[asm|dis|opc]-2.c files.
+ Test cases to cover new instruction assembling and disassembling.

For more details regarding DSB memory barrier instruction and its
Armv8.7-a flavour please refer to Arm A64 Instruction set documentation
for Armv8-A architecture profile, see document pages 132-133 of [0].

	[0]: https://developer.arm.com/docs/ddi0596/i

gas/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <[email protected]>

	* NEWS: Docs update.
	* config/tc-aarch64.c (parse_operands): Add
	AARCH64_OPND_BARRIER_DSB_NXS handler.
	(md_begin): Add content of aarch64_barrier_dsb_nxs_options to
	aarch64_barrier_opt_hsh hash.
	* testsuite/gas/aarch64/system-4-invalid.d: New test.
	* testsuite/gas/aarch64/system-4-invalid.l: New test.
	* testsuite/gas/aarch64/system-4-invalid.s: New test.
	* testsuite/gas/aarch64/system-4.d: New test.
	* testsuite/gas/aarch64/system-4.s: New test.

include/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <[email protected]>

	* opcode/aarch64.h (enum aarch64_opnd): New operand
	AARCH64_OPND_BARRIER_DSB_NXS.
	(aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.

opcodes/ChangeLog:

2020-10-23  Przemyslaw Wirkus  <[email protected]>

	* aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
	* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
	ins_barrier_dsb_nx.
	* aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
	* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
	ext_barrier_dsb_nx.
	* aarch64-opc.c (aarch64_print_operand): New options table
	aarch64_barrier_dsb_nxs_options.
	* aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
	* aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
	Armv8.7-a instruction.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

gas/NEWS

@@ -21,6 +21,8 @@
 
 * Add support for Armv8-R and Armv8.7-A AArch64.
 
+* Add support for DSB memory nXS barrier instruction for Armv8.7 AArch64.
+
 * Add support for Intel TDX instructions.
 
 * Add support for Intel Key Locker instructions.

gas/config/tc-aarch64.c

@@ -6686,12 +6686,49 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	      backtrack_pos = 0;
 	      goto failure;
 	    }
+	  if (val != PARSE_FAIL
+	      && operands[i] == AARCH64_OPND_BARRIER)
+	    {
+	      /* Regular barriers accept options CRm (C0-C15).
+	         DSB nXS barrier variant accepts values > 15.  */
+	      po_imm_or_fail (0, 15);
+	    }
 	  /* This is an extension to accept a 0..15 immediate.  */
 	  if (val == PARSE_FAIL)
 	    po_imm_or_fail (0, 15);
 	  info->barrier = aarch64_barrier_options + val;
 	  break;
 
+	case AARCH64_OPND_BARRIER_DSB_NXS:
+	  val = parse_barrier (&str);
+	  if (val != PARSE_FAIL)
+	    {
+	      /* DSB nXS barrier variant accept only <option>nXS qualifiers.  */
+	      if (!(val == 16 || val == 20 || val == 24 || val == 28))
+	        {
+	          set_syntax_error (_("the specified option is not accepted in DSB"));
+	          /* Turn off backtrack as this optional operand is present.  */
+	          backtrack_pos = 0;
+	          goto failure;
+	        }
+	    }
+	  else
+	    {
+	      /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
+	         possible values 16, 20, 24 or 28 , encoded as val<3:2>.  */
+	      if (! parse_constant_immediate (&str, &val, imm_reg_type))
+	        goto failure;
+	      if (!(val == 16 || val == 20 || val == 24 || val == 28))
+	        {
+	          set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
+	          goto failure;
+	        }
+	    }
+	  /* Option index is encoded as 2-bit value in val<3:2>.  */
+	  val = (val >> 2) - 4;
+	  info->barrier = aarch64_barrier_dsb_nxs_options + val;
+	  break;
+
 	case AARCH64_OPND_PRFOP:
 	  val = parse_pldop (&str);
 	  /* This is an extension to accept a 0..31 immediate.  */
@@ -8782,6 +8819,16 @@ md_begin (void)
 			   (void *) (aarch64_barrier_options + i));
     }
 
+  for (i = 0; i < ARRAY_SIZE (aarch64_barrier_dsb_nxs_options); i++)
+    {
+      const char *name = aarch64_barrier_dsb_nxs_options[i].name;
+      checked_hash_insert (aarch64_barrier_opt_hsh, name,
+			   (void *) (aarch64_barrier_dsb_nxs_options + i));
+      /* Also hash the name in the upper case.  */
+      checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
+			   (void *) (aarch64_barrier_dsb_nxs_options + i));
+    }
+
   for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
     {
       const char* name = aarch64_prfops[i].name;

gas/testsuite/gas/aarch64/system-4-invalid.d

@@ -0,0 +1,3 @@
+#name: Invalid DSB memory nXS barrier variant
+#source: system-4-invalid.s
+#error_output: system-4-invalid.l

gas/testsuite/gas/aarch64/system-4-invalid.l

@@ -0,0 +1,11 @@
+.*: Assembler messages:
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #17'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #18'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #19'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #21'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #22'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #23'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #25'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #26'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #27'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #29'

gas/testsuite/gas/aarch64/system-4-invalid.s

@@ -0,0 +1,16 @@
+/* Armv8.7-a DSB memory nXS barrier variant.  */
+.arch armv8.7-a
+
+    dsb #17
+    dsb #18
+    dsb #19
+
+    dsb #21
+    dsb #22
+    dsb #23
+
+    dsb #25
+    dsb #26
+    dsb #27
+
+    dsb #29

gas/testsuite/gas/aarch64/system-4.d

@@ -0,0 +1,16 @@
+#name: DSB memory nXS barrier variant
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d503323f 	dsb	oshnxs
+.*:	d503363f 	dsb	nshnxs
+.*:	d5033a3f 	dsb	ishnxs
+.*:	d5033e3f 	dsb	synxs
+.*:	d503323f 	dsb	oshnxs
+.*:	d503363f 	dsb	nshnxs
+.*:	d5033a3f 	dsb	ishnxs
+.*:	d5033e3f 	dsb	synxs

gas/testsuite/gas/aarch64/system-4.s

@@ -0,0 +1,12 @@
+/* Armv8.7-a DSB memory nXS barrier variant.  */
+.arch armv8.7-a
+
+    dsb #16
+    dsb #20
+    dsb #24
+    dsb #28
+
+    dsb oshnxs
+    dsb nshnxs
+    dsb ishnxs
+    dsb synxs

include/opcode/aarch64.h

@@ -317,6 +317,7 @@ enum aarch64_opnd
   AARCH64_OPND_SYSREG_TLBI,	/* System register <tlbi_op> operand.  */
   AARCH64_OPND_SYSREG_SR,	/* System register RCTX operand.  */
   AARCH64_OPND_BARRIER,		/* Barrier operand.  */
+  AARCH64_OPND_BARRIER_DSB_NXS,	/* Barrier operand for DSB nXS variant.  */
   AARCH64_OPND_BARRIER_ISB,	/* Barrier operand for ISB.  */
   AARCH64_OPND_PRFOP,		/* Prefetch operation.  */
   AARCH64_OPND_BARRIER_PSB,	/* Barrier operand for PSB.  */
@@ -949,6 +950,7 @@ struct aarch64_name_value_pair
 
 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
+extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 extern const struct aarch64_name_value_pair aarch64_hint_options [];