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[AArch64][SVE 27/32] Add SVE integer immediate operands
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This patch adds the new SVE integer immediate operands.  There are
three kinds:

- simple signed and unsigned ranges, but with new widths and positions.

- 13-bit logical immediates.  These have the same form as in base AArch64,
  but at a different bit position.

  In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
  immediate <limm> is not allowed to be a valid DUP immediate, since DUP
  is preferred over DUPM for constants that both instructions can handle.

- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
  In some contexts the operand is signed and in others it's unsigned.
  As an extension, we allow shifted immediates to be written as a single
  integer, e.g. "#256" is equivalent to "#1, LSL #8".  We also use the
  shiftless form as the preferred disassembly, except for the special
  case of "#0, LSL #8" (a redundant encoding of 0).

include/
	* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
	(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
	(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
	(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
	(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
	(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
	(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
	(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
	(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
	(AARCH64_OPND_SVE_UIMM8_53): Likewise.
	(aarch64_sve_dupm_mov_immediate_p): Declare.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
	integer immediate operands.
	* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
	(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
	(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries.
	(operand_general_constraint_met_p): Handle the new SVE integer
	immediate operands.
	(aarch64_print_operand): Likewise.
	(aarch64_sve_dupm_mov_immediate_p): New function.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
	(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
	* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
	(aarch64_ins_limm): ...here.
	(aarch64_ins_inv_limm): New function.
	(aarch64_ins_sve_aimm): Likewise.
	(aarch64_ins_sve_asimm): Likewise.
	(aarch64_ins_sve_limm_mov): Likewise.
	(aarch64_ins_sve_shlimm): Likewise.
	(aarch64_ins_sve_shrimm): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
	(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
	* aarch64-dis.c (decode_limm): New function, split out from...
	(aarch64_ext_limm): ...here.
	(aarch64_ext_inv_limm): New function.
	(decode_sve_aimm): Likewise.
	(aarch64_ext_sve_aimm): Likewise.
	(aarch64_ext_sve_asimm): Likewise.
	(aarch64_ext_sve_limm_mov): Likewise.
	(aarch64_top_bit): Likewise.
	(aarch64_ext_sve_shlimm): Likewise.
	(aarch64_ext_sve_shrimm): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
	immediate operands.
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@rsandifo-arm
rsandifo-arm committed Sep 21, 2016
1 parent 98907a7 commit e950b34
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5 changes: 5 additions & 0 deletions gas/ChangeLog
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Original file line number Diff line number Diff line change
@@ -1,3 +1,8 @@
2016-09-21 Richard Sandiford <[email protected]>

* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.

2016-09-21 Richard Sandiford <[email protected]>

* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
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27 changes: 27 additions & 0 deletions gas/config/tc-aarch64.c
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Expand Up @@ -5501,17 +5501,44 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;

case AARCH64_OPND_CCMP_IMM:
case AARCH64_OPND_SIMM5:
case AARCH64_OPND_FBITS:
case AARCH64_OPND_UIMM4:
case AARCH64_OPND_UIMM3_OP1:
case AARCH64_OPND_UIMM3_OP2:
case AARCH64_OPND_IMM_VLSL:
case AARCH64_OPND_IMM:
case AARCH64_OPND_WIDTH:
case AARCH64_OPND_SVE_INV_LIMM:
case AARCH64_OPND_SVE_LIMM:
case AARCH64_OPND_SVE_LIMM_MOV:
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
case AARCH64_OPND_SVE_SHRIMM_PRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED:
case AARCH64_OPND_SVE_SIMM5:
case AARCH64_OPND_SVE_SIMM5B:
case AARCH64_OPND_SVE_SIMM6:
case AARCH64_OPND_SVE_SIMM8:
case AARCH64_OPND_SVE_UIMM3:
case AARCH64_OPND_SVE_UIMM7:
case AARCH64_OPND_SVE_UIMM8:
case AARCH64_OPND_SVE_UIMM8_53:
po_imm_nc_or_fail ();
info->imm.value = val;
break;

case AARCH64_OPND_SVE_AIMM:
case AARCH64_OPND_SVE_ASIMM:
po_imm_nc_or_fail ();
info->imm.value = val;
skip_whitespace (str);
if (skip_past_comma (&str))
po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
else
inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
break;

case AARCH64_OPND_SVE_PATTERN:
po_enum_or_fail (aarch64_sve_pattern_array);
info->imm.value = val;
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14 changes: 14 additions & 0 deletions include/ChangeLog
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Original file line number Diff line number Diff line change
@@ -1,3 +1,17 @@
2016-09-21 Richard Sandiford <[email protected]>

* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.

2016-09-21 Richard Sandiford <[email protected]>

* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
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21 changes: 21 additions & 0 deletions include/opcode/aarch64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -200,6 +200,7 @@ enum aarch64_opnd
AARCH64_OPND_BIT_NUM, /* Immediate. */
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
each condition flag. */

Expand Down Expand Up @@ -289,6 +290,11 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
Expand All @@ -300,6 +306,18 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
Expand Down Expand Up @@ -1065,6 +1083,9 @@ aarch64_get_operand_name (enum aarch64_opnd);
extern const char *
aarch64_get_operand_desc (enum aarch64_opnd);

extern bfd_boolean
aarch64_sve_dupm_mov_immediate_p (uint64_t, int);

#ifdef DEBUG_AARCH64
extern int debug_dump;

Expand Down
38 changes: 38 additions & 0 deletions opcodes/ChangeLog
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Original file line number Diff line number Diff line change
@@ -1,3 +1,41 @@
2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
Expand Down
100 changes: 62 additions & 38 deletions opcodes/aarch64-asm-2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -480,12 +480,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27:
case 35:
case 36:
case 129:
case 130:
case 131:
case 132:
case 133:
case 134:
case 135:
case 136:
case 137:
Expand All @@ -494,7 +488,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 140:
case 141:
case 142:
case 145:
case 155:
case 156:
case 157:
case 158:
case 159:
case 160:
case 163:
return aarch64_ins_regno (self, info, code, inst);
case 12:
return aarch64_ins_reg_extended (self, info, code, inst);
Expand Down Expand Up @@ -527,12 +527,21 @@ aarch64_insert_operand (const aarch64_operand *self,
case 56:
case 57:
case 58:
case 67:
case 59:
case 68:
case 69:
case 70:
case 126:
case 128:
case 71:
case 132:
case 134:
case 147:
case 148:
case 149:
case 150:
case 151:
case 152:
case 153:
case 154:
return aarch64_ins_imm (self, info, code, inst);
case 38:
case 39:
Expand All @@ -543,61 +552,61 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
case 46:
return aarch64_ins_fpimm (self, info, code, inst);
case 59:
return aarch64_ins_limm (self, info, code, inst);
case 60:
return aarch64_ins_aimm (self, info, code, inst);
case 130:
return aarch64_ins_limm (self, info, code, inst);
case 61:
return aarch64_ins_imm_half (self, info, code, inst);
return aarch64_ins_aimm (self, info, code, inst);
case 62:
return aarch64_ins_imm_half (self, info, code, inst);
case 63:
return aarch64_ins_fbits (self, info, code, inst);
case 64:
case 65:
case 66:
return aarch64_ins_cond (self, info, code, inst);
case 71:
case 77:
return aarch64_ins_addr_simple (self, info, code, inst);
case 72:
return aarch64_ins_addr_regoff (self, info, code, inst);
case 78:
return aarch64_ins_addr_simple (self, info, code, inst);
case 73:
return aarch64_ins_addr_regoff (self, info, code, inst);
case 74:
case 75:
return aarch64_ins_addr_simm (self, info, code, inst);
case 76:
return aarch64_ins_addr_simm (self, info, code, inst);
case 77:
return aarch64_ins_addr_uimm12 (self, info, code, inst);
case 78:
return aarch64_ins_simd_addr_post (self, info, code, inst);
case 79:
return aarch64_ins_sysreg (self, info, code, inst);
return aarch64_ins_simd_addr_post (self, info, code, inst);
case 80:
return aarch64_ins_pstatefield (self, info, code, inst);
return aarch64_ins_sysreg (self, info, code, inst);
case 81:
return aarch64_ins_pstatefield (self, info, code, inst);
case 82:
case 83:
case 84:
return aarch64_ins_sysins_op (self, info, code, inst);
case 85:
return aarch64_ins_sysins_op (self, info, code, inst);
case 86:
return aarch64_ins_barrier (self, info, code, inst);
case 87:
return aarch64_ins_prfop (self, info, code, inst);
return aarch64_ins_barrier (self, info, code, inst);
case 88:
return aarch64_ins_hint (self, info, code, inst);
return aarch64_ins_prfop (self, info, code, inst);
case 89:
return aarch64_ins_hint (self, info, code, inst);
case 90:
case 91:
case 92:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
case 93:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
case 94:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
case 95:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
case 96:
case 97:
case 98:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
case 99:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
case 100:
case 101:
case 102:
Expand All @@ -609,33 +618,48 @@ aarch64_insert_operand (const aarch64_operand *self,
case 108:
case 109:
case 110:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 111:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 112:
case 113:
case 114:
case 115:
case 116:
case 117:
case 118:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 119:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 120:
case 121:
case 122:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
case 123:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
case 124:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
case 125:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
case 126:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
case 127:
return aarch64_ins_sve_aimm (self, info, code, inst);
case 128:
return aarch64_ins_sve_asimm (self, info, code, inst);
case 129:
return aarch64_ins_inv_limm (self, info, code, inst);
case 131:
return aarch64_ins_sve_limm_mov (self, info, code, inst);
case 133:
return aarch64_ins_sve_scale (self, info, code, inst);
case 143:
return aarch64_ins_sve_index (self, info, code, inst);
case 144:
return aarch64_ins_sve_shlimm (self, info, code, inst);
case 145:
case 146:
return aarch64_ins_sve_shrimm (self, info, code, inst);
case 161:
return aarch64_ins_sve_index (self, info, code, inst);
case 162:
case 164:
return aarch64_ins_sve_reglist (self, info, code, inst);
default: assert (0); abort ();
}
Expand Down
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