RISC-V: Support Zcmp push/pop instructions.

Support zcmp extension push/pop/popret and popret zero instructions.
The `reg_list' is a list containing 1 to 13 registers, we can use:
"{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}"
to present this feature.

Passed gcc/binutils regressions of riscv-gnu-toolchain.

Most of work was finished by Sinan Lin.
Co-Authored by: Charlie Keaney <[email protected]>
Co-Authored by: Mary Bennett <[email protected]>
Co-Authored by: Nandni Jamnadas <[email protected]>
Co-Authored by: Sinan Lin <[email protected]>
Co-Authored by: Simon Cook <[email protected]>
Co-Authored by: Shihua Liao <[email protected]>
Co-Authored by: Yulong Shi <[email protected]>

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp.
	(riscv_supported_std_z_ext): Added zcmp with version 1.0.
	(riscv_parse_check_conflicts): Zcmp conflicts with d/zcd.
        (riscv_multi_subset_supports): Handle zcmp.
        (riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
        * config/tc-riscv.c (regno_to_reg_list): New function, used to map
	register to reg_list number.
        (reglist_lookup): Called reglist_lookup_internal.  Return false if
	reg_list number is zero, which is an invalid value.
	(reglist_lookup_internal): Parse register list, and return the last
	register by regno_to_reg_list.
        (validate_riscv_insn):  New operators.
        (riscv_ip): Ditto.
	* testsuite/gas/riscv/march-help.l: Updated.
        * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test.
        * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test.
        * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test.
        * testsuite/gas/riscv/zcmp-push-pop.d: New test.
        * testsuite/gas/riscv/zcmp-push-pop.s: New test.

include/ChangeLog:

        * opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp.
        (MATCH/MASK_CM_POP): Ditto.
        (MATCH/MASK_CM_POPRET): Ditto.
        (MATCH/MASK_CM_POPRETZ): Ditto.
        (DECLARE_INSN): New declarations for zcmp.
        * opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm
	operand for zcmp.
        (OP_MASK_REG_LIST): Handle operand for zcmp register list.
        (OP_SH_REG_LIST): Ditto.
        (ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base.
        (X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers.
        (enum riscv_insn_class): Added INSN_CLASS_ZCMP.
        (extern riscv_get_sp_base): Added.

opcodes/ChangeLog:

        * riscv-dis.c (print_reg_list): New function, used to get zcmp
	reg_list field.
        (riscv_get_spimm): New function, used to get zcmp sp adjustment
	immediate.
        (print_insn_args): Handle new operands for zcmp.
        * riscv-opc.c (riscv_get_sp_base): New function, used by gas and
	objdump.  Get sp base adjustment.
	(riscv_opcodes): Added zcmp instructions.

bfd/elfxx-riscv.c

@@ -1267,6 +1267,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcf", "zca",	check_implicit_always},
   {"zcd", "zca",	check_implicit_always},
   {"zcb", "zca",	check_implicit_always},
+  {"zcmp", "zca",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smcntrpmf", "zicsr",	check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
@@ -1415,6 +1416,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zcb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zcf",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zcd",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zcmp",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2056,6 +2058,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
       rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
       no_conflict = false;
     }
+  if (riscv_subset_supports (rps, "zcmp")
+      && riscv_subset_supports (rps, "zcd"))
+    {
+      rps->error_handler
+	(_("zcmp' is incompatible with `d/zcd' extension"));
+      no_conflict = false;
+    }
   if (riscv_lookup_subset (rps->subset_list, "zcf", &subset)
       && xlen > 32)
     {
@@ -2645,6 +2654,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return (riscv_subset_supports (rps, "zcb")
 	      && riscv_subset_supports (rps, "zmmul"));
+    case INSN_CLASS_ZCMP:
+      return riscv_subset_supports (rps, "zcmp");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2899,6 +2910,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zcb' and `zbb");
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return _("zcb' and `zmmul', or `zcb' and `m");
+    case INSN_CLASS_ZCMP:
+      return "zcmp";
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:

gas/NEWS

@@ -11,6 +11,8 @@
 * Remove support for RISC-V privileged spec 1.9.1, but linker can still
   recognize it in case of linking old objects.
 
+* Add support for RISC-V Zcmp extension with version 1.0.
+
 * The base register operand in D(X,B) and D(L,B) may be explicitly omitted
   in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
   D(X,%r0), D(L,0), and D(L,%r0).

gas/config/tc-riscv.c

@@ -1254,6 +1254,158 @@ flt_lookup (float f, const float *array, size_t size, unsigned *regnop)
   return false;
 }
 
+/* Map ra and s-register to [4,15], so that we can check if the
+   reg2 in register list reg1-reg2 or single reg2 is valid or not,
+   and obtain the corresponding reg_list value.
+
+   ra - 4
+   s0 - 5
+   s1 - 6
+    ....
+   s10 - 0 (invalid)
+   s11 - 15.  */
+
+static int
+regno_to_reg_list (unsigned regno)
+{
+  if (regno == X_RA)
+    return 4;
+  else if (regno == X_S0 || regno == X_S1)
+    return 5 + regno - X_S0;
+  else if (regno >= X_S2 && regno < X_S10)
+    return 7 + regno - X_S2;
+  else if (regno == X_S11)
+    return 15;
+
+  /* Invalid symbol.  */
+  return 0;
+}
+
+/* Parse register list, and return the last register by regno_to_reg_list.
+
+   If ABI register names are used (e.g. ra and s0), the register
+   list could be "{ra}", "{ra, s0}", "{ra, s0-sN}", where 0 < N < 10 or
+   N == 11.
+
+   If numeric register names are used (e.g. x1 and x8), the register list
+   could be "{x1}", "{x1,x8}", "{x1,x8-x9}", "{x1,x8-x9,x18}" and
+   "{x1,x8-x9,x18-xN}", where 19 < N < 25 or N == 27.
+
+   The numeric and ABI register names cannot be used at the same time.
+
+   TODO: Report errors for the following cases,
+   1. Too many registers in the list.
+   2. Cases which return 0.
+   3. Illegal formats, for example, {x1,x8-NULL,x18-x24/x18}, {x1-x2,x8}.  */
+
+static unsigned
+reglist_lookup_internal (char *reglist)
+{
+  unsigned regno = 0;
+  unsigned reg_list = 0;
+  char *regname[3][2] = {{NULL}};
+  char *save_tok, *save_subtok;
+  unsigned i, j;
+
+  char *token = strtok_r (reglist, ",", &save_tok);
+  for (i = 0; i < 3 && token != NULL;
+       token = strtok_r (NULL, ",", &save_tok), i++)
+    {
+      char *subtoken = strtok_r (token, "-", &save_subtok);
+      for (j = 0; j < 2 && subtoken != NULL;
+	   subtoken = strtok_r (NULL, "-", &save_subtok), j++)
+	regname[i][j] = subtoken;
+    }
+
+  bool reg1_numeric = false;
+  for (i = 0; i < 3; i++)
+    {
+      if (regname[i][0] == NULL)
+	continue;
+#define REG_TO_REG_LIST(NAME, NUM, LIST) \
+  (reg_lookup (&NAME, RCLASS_GPR, &NUM) && (LIST = regno_to_reg_list (NUM)))
+#define REG_NUMERIC(NAME) (NAME[0] == 'x')
+#define REG_CONFLICT(NAME, REG_NUMERIC) \
+  ((NAME[0] == 'x' && !REG_NUMERIC) || (NAME[0] != 'x' && REG_NUMERIC))
+      switch (i)
+	{
+	case 0:
+	  reg1_numeric = REG_NUMERIC (regname[i][0]);
+	  if (!REG_TO_REG_LIST (regname[i][0], regno, reg_list)
+	      || regno != X_RA)
+	    return 0;
+	  break;
+	case 1:
+	  if (REG_CONFLICT (regname[i][0], reg1_numeric)
+	      /* The second register should be s0 or its numeric names x8.  */
+	      || !REG_TO_REG_LIST (regname[i][0], regno, reg_list)
+	      || regno != X_S0)
+	    return 0;
+	  else if (regname[i][1] == NULL)
+	    return reg_list;
+
+	  if (REG_CONFLICT (regname[i][1], reg1_numeric)
+	      /* The third register is x9 if the numeric name is used.
+		 Otherwise, it could be any other sN register, where N > 0.  */
+	      || !REG_TO_REG_LIST (regname[i][1], regno, reg_list)
+	      || regno <= X_S0
+	      || (reg1_numeric && regno != X_S1))
+	    return 0;
+	  break;
+	case 2:
+	  /* Must use register numeric names.  */
+	  if (!reg1_numeric
+	      || !REG_NUMERIC (regname[i][0])
+	      /* The fourth register should be s2.  */
+	      || !REG_TO_REG_LIST (regname[i][0], regno, reg_list)
+	      || regno != X_S2)
+	    return 0;
+	  else if (regname[i][1] == NULL)
+	    return reg_list;
+
+	  if (!reg1_numeric
+	      || !REG_NUMERIC (regname[i][1])
+	      /* The fifth register could be any other sN register, where N > 1.  */
+	      || !REG_TO_REG_LIST (regname[i][1], regno, reg_list)
+	      || regno <= X_S2)
+	    return 0;
+	  break;
+	default:
+	  return 0;
+	}
+#undef REG_TO_REG_LIST
+#undef REG_NUMERIC
+#undef REG_CONFLICT
+    }
+  return reg_list;
+}
+
+/* Parse register list.  Return false if REG_LIST is zero, which is an
+   invalid value.  */
+
+static bool
+reglist_lookup (char **s, unsigned *reg_list)
+{
+  *reg_list = 0;
+  char *reglist = strdup (*s);
+  if (reglist != NULL)
+    {
+      char *token = strtok (reglist, "}");
+      if (token != NULL)
+	{
+	  *s += strlen (token);
+	  *reg_list = reglist_lookup_internal (reglist);
+	}
+      else
+	{
+	  as_bad (_("cannot find `}' for cm.push/cm.pop"));
+	  *reg_list = 0;
+	}
+    }
+  free (reglist);
+  return *reg_list == 0 ? false : true;
+}
+
 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
 #define USE_IMM(n, s) \
   (used_bits |= ((insn_t)((1ull<<n)-1) << (s)))
@@ -1370,6 +1522,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	case ',': break;
 	case '(': break;
 	case ')': break;
+	case '{': break;
+	case '}': break;
 	case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
 	case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
 	case 'A': break; /* Macro operand, must be symbol.  */
@@ -1450,6 +1604,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break;
 		/* halfword immediate operators, load/store halfword insns.  */
 		case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break;
+		/* Immediate offset operand for cm.push and cm.pop.  */
+		case 'p': used_bits |= ENCODE_ZCMP_SPIMM (-1U); break;
+		/* Register list operand for cm.push and cm.pop.  */
+		case 'r': USE_BITS (OP_MASK_REG_LIST, OP_SH_REG_LIST); break;
 		case 'f': break;
 		default:
 		  goto unknown_validate_operand;
@@ -3206,6 +3364,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	    case ')':
 	    case '[':
 	    case ']':
+	    case '{':
+	    case '}':
 	      if (*asarg++ == *oparg)
 		continue;
 	      break;
@@ -3661,6 +3821,27 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 			break;
 		      ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number);
 		      goto rvc_imm_done;
+		    case 'r':
+		      if (!reglist_lookup (&asarg, &regno))
+			break;
+		      INSERT_OPERAND (REG_LIST, *ip, regno);
+		      continue;
+		    case 'p':
+		      if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
+			|| imm_expr->X_op != O_constant)
+			break;
+		      /* Convert stack adjustment of cm.push to a positive
+			 offset.  */
+		      if (ip->insn_mo->match == MATCH_CM_PUSH)
+			imm_expr->X_add_number *= -1;
+		      /* Subtract base stack adjustment and get spimm.  */
+		      imm_expr->X_add_number -=
+			riscv_get_sp_base (ip->insn_opcode, *riscv_rps_as.xlen);
+		      if (!VALID_ZCMP_SPIMM (imm_expr->X_add_number))
+			break;
+		      ip->insn_opcode |=
+			ENCODE_ZCMP_SPIMM (imm_expr->X_add_number);
+		      goto rvc_imm_done;
 		    case 'f': /* Operand for matching immediate 255.  */
 		      if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
 			  || imm_expr->X_op != O_constant

gas/testsuite/gas/riscv/march-help.l

@@ -87,6 +87,7 @@ All available -march extensions for RISC-V:
 	zcb                                     1.0
 	zcf                                     1.0
 	zcd                                     1.0
+	zcmp                                    1.0
 	smaia                                   1.0
 	smcntrpmf                               1.0
 	smepmp                                  1.0

gas/testsuite/gas/riscv/zcmp-push-pop-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv64i_zcmp
+#source: zcmp-push-pop-fail.s
+#error_output: zcmp-push-pop-fail.l

gas/testsuite/gas/riscv/zcmp-push-pop-fail.l

@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cm.push \{a0\},-64'
+.*: Error: illegal operands `cm.pop \{ra,s1\},-64'
+.*: Error: illegal operands `cm.popret \{ra,s2-s3\},-64'
+.*: Error: illegal operands `cm.popretz \{ra,s0-s10\},-112'
+.*: Error: illegal operands `cm.push \{ra\},0'
+.*: Error: illegal operands `cm.pop \{ra,s0\},-80'
+.*: Error: illegal operands `cm.popret \{ra,s0-s1\},-15'
+.*: Error: illegal operands `cm.popretz \{ra,s0-s11\},-165'

gas/testsuite/gas/riscv/zcmp-push-pop-fail.s

@@ -0,0 +1,13 @@
+target:
+
+	# reg_list
+	cm.push {a0}, -64
+	cm.pop {ra, s1}, -64
+	cm.popret {ra, s2-s3}, -64
+	cm.popretz {ra, s0-s10}, -112
+
+	# spimm
+	cm.push {ra}, 0
+	cm.pop {ra, s0}, -80
+	cm.popret {ra, s0-s1}, -15
+	cm.popretz {ra, s0-s11}, -165