Clarification about skip instructions

See trillek-team/trillek-vcomputer-module#56
trillek-team · Feb 19, 2015 · defccac · defccac
1 parent 36b3649
commit defccac
Showing 1 changed file with 7 additions and 5 deletions.
diff --git a/cpu/TR3200.md b/cpu/TR3200.md
@@ -5,7 +5,7 @@ cat : CPU
 ---
 TR3200 (Trillek Risc cpu 32 00) Specification
 ====================================
-Version 0.4.1 
+Version 0.4.2 
 
 
 SUMMARY
@@ -554,14 +554,16 @@ Y = Rs % Rn
 SKIP OPERATIONS
 --------------------
 
-  The skip instructions, realizes a comparison between two values If the test
+  The skip instructions, realizes a comparison between two values. If the test
   fails, the next instruction is skiped. The conditional opcodes take one cycle
   longer to perform if the test fails.
 
   When they skip a conditional instruction, they will skip an additional
-  instruction at the cost of one extra cycle. This continues until a non-
-  conditional instruction has been skipped. This lets you easily chain
-  conditionals. Interrupts are not triggered while the TR3200 is skipping.
+  instruction at the cost of one extra cycle. If the skiped instruction have a 
+  long literal, the costs keeps being a single cyle, becase the CPU can check 
+  M and L bits without penaly. This continues until a non-conditional 
+  instruction has been skipped. This lets you easily chain conditionals. 
+  Interrupts are not triggered while the TR3200 is skipping.
 
 
     IFEQ Rd, Rn      Executes next if Rd == Rn