TCL (Tool Command Language) is a programming language that is commonly used in VLSI (Very-Large-Scale Integration) to automate and script various tasks in design flow. It can be used to create scripts that automate the execution of commands in various CAD tools, such as synthesis and place-and-route tools. It can also be used to create custom scripts for tasks such as floorplanning, power analysis, and timing closure. The use of TCL allows engineers to streamline their workflows, increase productivity, and reduce human errors.
In this workshop, Synthesis is performed using Yosys
STA analysis using OpenTimer 1.0.5
1.CSV File is not provided
2.CSV File is not existed in the format
3.helps the user for options
- Creating the variables
-
Checking the directory or file exist in the path
1.Creating SDC file with clock constraints
File created in the output directory
- INPUT PORTS Constraints in SDC file
- OUTPUT CONSTRAINTS in the SDC file
-
Memory design and Synthesized result in YOSYS
-
Synthesized netlist of memory design
-
Hierarchy check with Error
5.Hierarchy check without error
-
Synthesis stopped with error
-
Synthesis finished successfully
-
Snapshot of the generated timing file
-
Snapshot of .result file
-
QOR Result obtained
