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[VTA] Refactor to increase platform coverage (Ultra96 etc.) (apache#3496
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* hardware refactor for increased FPGA coverage, small optimizations

* fix header

* cleaning up parameters that won't be needed for now

* streamlining makefile, and simplifying tcl scripts

* moving parameter derivation into pkg_config.py, keeping tcl scripts lightweight

* refactoring tcl script to avoid global variables

* deriving AXI signals in pkg_config.py

* unifying address map definition for hardware and software drivers

* single channel design for ultra96 to simplify build

* enable alu by default, no mul opcode for now

* hardware fix

* new bitstream; vta version

* avoid error when env variable is not set

* ultra96 cleanup

* further cleaning up tcl script for bitstream generation

* preliminary rpc server support on ultra96

* rpc server tracker scripts

* ultra96 ldflag

* ultra96 support

* ultra96 support

* cleanup line

* cmake support for ultra96

* simplify memory instantiation

* cleaning up IP parameter initialization

* fix queue instantiation

* 2019.1 transition

* fix macro def

* removing bus width from config

* cleanup

* fix

* turning off testing for now

* cleanup ultra96 ps insantiation

* minor refactor

* adding comments

* upgrading to tophub v0.6

* model used in TVM target now refers to a specific version of VTA for better autoTVM scheduling

* revert change due to bug

* rename driver files to be for zynq-type devices

* streamlining address mapping

* unifying register map offset values between driver and hardware generator

* rely on cma library for cache flush/invalidation

* coherence management

* not make buffer packing depend on data types that can be wider than 64bits

* refactor config derivation to minimize free parameters

* fix environment/pkg config interaction

* adding cfg dump property to pkgconfig:

* fix rpc reconfig

* fix spacing

* cleanup

* fix spacing

* long line fix

* fix spacing and lint

* fix line length

* cmake fix

* environment fix

* renaming after pynq since the driver stack relies on the pynq library - see pynq.io

* update doc

* adding parameterization to  name

* space

* removing reg width

* vta RPC

* update doc on how to edit vta_config.json

* fix path

* fix path
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@tmoreau89 @jroesch
tmoreau89 authored and jroesch committed Jul 29, 2019
1 parent 0917860 commit dd4ca23
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Showing 27 changed files with 1,576 additions and 2,291 deletions.
10 changes: 3 additions & 7 deletions config/pynq_sample.json
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Original file line number Diff line number Diff line change
@@ -1,17 +1,13 @@
{
"TARGET" : "pynq",
"HW_FREQ" : 100,
"HW_CLK_TARGET" : 8,
"HW_VER" : "0.0.0",
"HW_VER" : "0.0.1",
"LOG_INP_WIDTH" : 3,
"LOG_WGT_WIDTH" : 3,
"LOG_ACC_WIDTH" : 5,
"LOG_OUT_WIDTH" : 3,
"LOG_BATCH" : 0,
"LOG_BLOCK_IN" : 4,
"LOG_BLOCK_OUT" : 4,
"LOG_BLOCK" : 4,
"LOG_UOP_BUFF_SIZE" : 15,
"LOG_INP_BUFF_SIZE" : 15,
"LOG_INP_BUFF_SIZE" :15,
"LOG_WGT_BUFF_SIZE" : 18,
"LOG_ACC_BUFF_SIZE" : 17
}
13 changes: 13 additions & 0 deletions config/ultra96_sample.json
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Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
{
"TARGET" : "ultra96",
"HW_VER" : "0.0.1",
"LOG_INP_WIDTH" : 3,
"LOG_WGT_WIDTH" : 3,
"LOG_ACC_WIDTH" : 5,
"LOG_BATCH" : 0,
"LOG_BLOCK" : 4,
"LOG_UOP_BUFF_SIZE" : 15,
"LOG_INP_BUFF_SIZE" :15,
"LOG_WGT_BUFF_SIZE" : 18,
"LOG_ACC_BUFF_SIZE" : 17
}
8 changes: 2 additions & 6 deletions config/vta_config.json
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Original file line number Diff line number Diff line change
@@ -1,15 +1,11 @@
{
"TARGET" : "sim",
"HW_FREQ" : 100,
"HW_CLK_TARGET" : 7,
"HW_VER" : "0.0.0",
"HW_VER" : "0.0.1",
"LOG_INP_WIDTH" : 3,
"LOG_WGT_WIDTH" : 3,
"LOG_ACC_WIDTH" : 5,
"LOG_OUT_WIDTH" : 3,
"LOG_BATCH" : 0,
"LOG_BLOCK_IN" : 4,
"LOG_BLOCK_OUT" : 4,
"LOG_BLOCK" : 4,
"LOG_UOP_BUFF_SIZE" : 15,
"LOG_INP_BUFF_SIZE" : 15,
"LOG_WGT_BUFF_SIZE" : 18,
Expand Down
185 changes: 106 additions & 79 deletions config/vta_config.py
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,6 @@ def get_pkg_config(cfg):
PkgConfig = libpkg["PkgConfig"]
return PkgConfig(cfg, proj_root)


def main():
"""Main funciton"""
parser = argparse.ArgumentParser()
Expand All @@ -45,7 +44,7 @@ def main():
parser.add_argument("--update", action="store_true",
help="Print out the json option.")
parser.add_argument("--ldflags", action="store_true",
help="print the cflags")
help="print the ldflags")
parser.add_argument("--cfg-json", action="store_true",
help="print all the config json")
parser.add_argument("--save-cfg-json", type=str, default="",
Expand All @@ -54,33 +53,51 @@ def main():
help="print the target")
parser.add_argument("--cfg-str", action="store_true",
help="print the configuration string")
parser.add_argument("--get-inpwidth", action="store_true",
help="returns log of input bitwidth")
parser.add_argument("--get-wgtwidth", action="store_true",
help="returns log of weight bitwidth")
parser.add_argument("--get-accwidth", action="store_true",
help="returns log of accum bitwidth")
parser.add_argument("--get-outwidth", action="store_true",
help="returns log of output bitwidth")
parser.add_argument("--get-batch", action="store_true",
help="returns log of tensor batch dimension")
parser.add_argument("--get-blockin", action="store_true",
help="returns log of tensor block in dimension")
parser.add_argument("--get-blockout", action="store_true",
help="returns log of tensor block out dimension")
parser.add_argument("--get-uopbuffsize", action="store_true",
help="returns log of micro-op buffer size in B")
parser.add_argument("--get-inpbuffsize", action="store_true",
help="returns log of input buffer size in B")
parser.add_argument("--get-wgtbuffsize", action="store_true",
help="returns log of weight buffer size in B")
parser.add_argument("--get-accbuffsize", action="store_true",
help="returns log of accum buffer size in B")
parser.add_argument("--get-outbuffsize", action="store_true",
help="returns log of output buffer size in B")
parser.add_argument("--get-fpgafreq", action="store_true",
parser.add_argument("--get-inp-mem-banks", action="store_true",
help="returns number of input memory banks")
parser.add_argument("--get-inp-mem-width", action="store_true",
help="returns input memory read/write port width")
parser.add_argument("--get-inp-mem-depth", action="store_true",
help="returns input memory depth")
parser.add_argument("--get-inp-mem-axi-ratio", action="store_true",
help="returns ratio between input element width and axi width")
parser.add_argument("--get-wgt-mem-banks", action="store_true",
help="returns number of weight memory banks")
parser.add_argument("--get-wgt-mem-width", action="store_true",
help="returns weight memory read/write port width")
parser.add_argument("--get-wgt-mem-depth", action="store_true",
help="returns weight memory depth")
parser.add_argument("--get-wgt-mem-axi-ratio", action="store_true",
help="returns ratio between weight element width and axi width")
parser.add_argument("--get-out-mem-banks", action="store_true",
help="returns number of output memory banks")
parser.add_argument("--get-out-mem-width", action="store_true",
help="returns output memory read/write port width")
parser.add_argument("--get-out-mem-depth", action="store_true",
help="returns output memory depth")
parser.add_argument("--get-out-mem-axi-ratio", action="store_true",
help="returns ratio between output element width and axi width")
parser.add_argument("--get-axi-cache-bits", action="store_true",
help="returns AXI system ARCACHE/AWCACHE hardcoded bit value")
parser.add_argument("--get-axi-prot-bits", action="store_true",
help="returns AXI system ARPROT/AWPROT hardcoded bit value")
parser.add_argument("--get-ip-reg-map-range", action="store_true",
help="returns ip register map address range")
parser.add_argument("--get-fetch-base-addr", action="store_true",
help="returns fetch module base address")
parser.add_argument("--get-load-base-addr", action="store_true",
help="returns load module base address")
parser.add_argument("--get-compute-base-addr", action="store_true",
help="returns compute module base address")
parser.add_argument("--get-store-base-addr", action="store_true",
help="returns store module base address")
parser.add_argument("--get-fpga-dev", action="store_true",
help="returns FPGA device target")
parser.add_argument("--get-fpga-family", action="store_true",
help="returns FPGA device family")
parser.add_argument("--get-fpga-freq", action="store_true",
help="returns FPGA frequency")
parser.add_argument("--get-fpgaper", action="store_true",
parser.add_argument("--get-fpga-per", action="store_true",
help="returns HLS target clock period")
args = parser.parse_args()

Expand All @@ -92,8 +109,6 @@ def main():
os.path.abspath(os.path.expanduser(__file__)))
proj_root = os.path.abspath(os.path.join(curr_path, "../../"))
path_list = [
os.path.join(proj_root, "vta_config.json"),
os.path.join(proj_root, "build", "vta_config.json"),
os.path.join(proj_root, "vta/config/vta_config.json")
]
if args.use_cfg:
Expand All @@ -102,14 +117,11 @@ def main():
if not ok_path_list:
raise RuntimeError("Cannot find config in %s" % str(path_list))
cfg = json.load(open(ok_path_list[0]))
cfg["LOG_OUT_BUFF_SIZE"] = (
cfg["LOG_ACC_BUFF_SIZE"] +
cfg["LOG_OUT_WIDTH"] -
cfg["LOG_ACC_WIDTH"])

pkg = get_pkg_config(cfg)

if args.target:
print(pkg.target)
print(pkg.TARGET)

if args.defs:
print(" ".join(pkg.macro_defs))
Expand All @@ -119,8 +131,10 @@ def main():

if args.cflags:
cflags_str = " ".join(pkg.cflags)
if cfg["TARGET"] == "pynq":
if pkg.TARGET == "pynq":
cflags_str += " -DVTA_TARGET_PYNQ"
if pkg.TARGET == "ultra96":
cflags_str += " -DVTA_TARGET_ULTRA96"
print(cflags_str)

if args.ldflags:
Expand All @@ -134,63 +148,76 @@ def main():
fo.write(pkg.cfg_json)

if args.cfg_str:
# Needs to match the BITSTREAM string in python/vta/environment.py
cfg_str = "{}x{}x{}_{}bx{}b_{}_{}_{}_{}_{}MHz_{}ns_v{}".format(
(1 << cfg["LOG_BATCH"]),
(1 << cfg["LOG_BLOCK_IN"]),
(1 << cfg["LOG_BLOCK_OUT"]),
(1 << cfg["LOG_INP_WIDTH"]),
(1 << cfg["LOG_WGT_WIDTH"]),
cfg["LOG_UOP_BUFF_SIZE"],
cfg["LOG_INP_BUFF_SIZE"],
cfg["LOG_WGT_BUFF_SIZE"],
cfg["LOG_ACC_BUFF_SIZE"],
cfg["HW_FREQ"],
cfg["HW_CLK_TARGET"],
cfg["HW_VER"].replace('.', '_'))
print(cfg_str)
print(pkg.TARGET + "_" + pkg.bitstream)

if args.get_inp_mem_banks:
print(pkg.inp_mem_banks)

if args.get_inp_mem_width:
print(pkg.inp_mem_width)

if args.get_inp_mem_depth:
print(pkg.inp_mem_depth)

if args.get_inp_mem_axi_ratio:
print(pkg.inp_mem_axi_ratio)

if args.get_wgt_mem_banks:
print(pkg.wgt_mem_banks)

if args.get_wgt_mem_width:
print(pkg.wgt_mem_width)

if args.get_wgt_mem_depth:
print(pkg.wgt_mem_depth)

if args.get_wgt_mem_axi_ratio:
print(pkg.wgt_mem_axi_ratio)

if args.get_out_mem_banks:
print(pkg.out_mem_banks)

if args.get_inpwidth:
print(cfg["LOG_INP_WIDTH"])
if args.get_out_mem_width:
print(pkg.out_mem_width)

if args.get_wgtwidth:
print(cfg["LOG_WGT_WIDTH"])
if args.get_out_mem_depth:
print(pkg.out_mem_depth)

if args.get_accwidth:
print(cfg["LOG_ACC_WIDTH"])
if args.get_out_mem_axi_ratio:
print(pkg.out_mem_axi_ratio)

if args.get_outwidth:
print(cfg["LOG_OUT_WIDTH"])
if args.get_axi_cache_bits:
print(pkg.axi_cache_bits)

if args.get_batch:
print(cfg["LOG_BATCH"])
if args.get_axi_prot_bits:
print(pkg.axi_prot_bits)

if args.get_blockin:
print(cfg["LOG_BLOCK_IN"])
if args.get_ip_reg_map_range:
print(pkg.ip_reg_map_range)

if args.get_blockout:
print(cfg["LOG_BLOCK_OUT"])
if args.get_fetch_base_addr:
print(pkg.fetch_base_addr)

if args.get_uopbuffsize:
print(cfg["LOG_UOP_BUFF_SIZE"])
if args.get_load_base_addr:
print(pkg.load_base_addr)

if args.get_inpbuffsize:
print(cfg["LOG_INP_BUFF_SIZE"])
if args.get_compute_base_addr:
print(pkg.compute_base_addr)

if args.get_wgtbuffsize:
print(cfg["LOG_WGT_BUFF_SIZE"])
if args.get_store_base_addr:
print(pkg.store_base_addr)

if args.get_outbuffsize:
print(cfg["LOG_OUT_BUFF_SIZE"])
if args.get_fpga_dev:
print(pkg.fpga_device)

if args.get_accbuffsize:
print(cfg["LOG_ACC_BUFF_SIZE"])
if args.get_fpga_family:
print(pkg.fpga_family)

if args.get_fpgafreq:
print(cfg["HW_FREQ"])
if args.get_fpga_freq:
print(pkg.fpga_freq)

if args.get_fpgaper:
print(cfg["HW_CLK_TARGET"])
if args.get_fpga_per:
print(pkg.fpga_per)

if __name__ == "__main__":
main()
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