[VTA] VTA hardware/software codebase re-org (apache#5037)

python/vta/environment.py

@@ -312,7 +312,7 @@ def _init_env():
         os.path.abspath(os.path.expanduser(__file__)))
     proj_root = os.path.abspath(os.path.join(curr_path, "../../../"))
     path_list = [
-        os.path.join(proj_root, "vta/config/vta_config.json")
+        os.path.join(proj_root, "vta/vta-hw/config/vta_config.json")
     ]
     path_list = [p for p in path_list if os.path.exists(p)]
     if not path_list:

python/vta/libinfo.py

@@ -40,7 +40,7 @@ def _get_lib_name(lib_name):
 
 
 def find_libvta(lib_vta, optional=False):
-    """Find VTA library
+    """Find VTA Chisel-based library
 
     Returns
     -------
@@ -56,10 +56,8 @@ def find_libvta(lib_vta, optional=False):
         Enable error check
     """
     curr_path = os.path.dirname(os.path.abspath(os.path.expanduser(__file__)))
-    lib_search = [curr_path]
-    lib_search += [os.path.join(curr_path, "..", "..", "build",)]
-    lib_search += [os.path.join(curr_path, "..", "..", "..", "build",)]
-    lib_search += [os.path.join(curr_path, "..", "..", "..", "build", "Release")]
+    lib_search = [os.path.join(curr_path, "..", "..", "..", "build",)]
+    lib_search += [os.path.join(curr_path, "..", "..", "vta-hw", "build")]
     lib_name = _get_lib_name(lib_vta)
     lib_path = [os.path.join(x, lib_name) for x in lib_search]
     lib_found = [x for x in lib_path if os.path.exists(x)]

python/vta/pkg_config.py

@@ -66,21 +66,21 @@ def __init__(self, cfg, proj_root):
         # Include path
         self.include_path = [
             "-I%s/include" % proj_root,
-            "-I%s/vta/include" % proj_root,
+            "-I%s/vta/vta-hw/include" % proj_root,
             "-I%s/3rdparty/dlpack/include" % proj_root,
             "-I%s/3rdparty/dmlc-core/include" % proj_root
         ]
 
         # List of source files that can be used to build standalone library.
         self.lib_source = []
-        self.lib_source += glob.glob("%s/vta/src/*.cc" % proj_root)
+        self.lib_source += glob.glob("%s/vta/vta-hw/src/*.cc" % proj_root)
         if self.TARGET in ["pynq", "ultra96"]:
             # add pynq drivers for any board that uses pynq driver stack (see pynq.io)
-            self.lib_source += glob.glob("%s/vta/src/pynq/*.cc" % (proj_root))
+            self.lib_source += glob.glob("%s/vta/vta-hw/src/pynq/*.cc" % (proj_root))
         elif self.TARGET in ["de10nano"]:
-            self.lib_source += glob.glob("%s/vta/src/de10nano/*.cc" % (proj_root))
+            self.lib_source += glob.glob("%s/vta/vta-hw/src/de10nano/*.cc" % (proj_root))
             self.include_path += [
-                "-I%s/vta/src/de10nano" % proj_root,
+                "-I%s/vta/vta-hw/src/de10nano" % proj_root,
                 "-I%s/3rdparty" % proj_root
             ]
 

python/vta/testing/simulator.py

@@ -37,7 +37,7 @@ def _load_sw():
 
     if env.TARGET == "tsim":
         lib_hw = find_libvta("libvta_hw", optional=True)
-        assert lib_hw # make sure to build vta/hardware/chisel
+        assert lib_hw # make sure to build vta/vta-hw/hardware/chisel
         try:
             f = tvm.get_global_func("vta.tsim.init")
             m = tvm.runtime.load_module(lib_hw[0], "vta-tsim")

src/device_api.cc → runtime/device_api.cc

@@ -24,8 +24,8 @@
 
 #include <tvm/runtime/registry.h>
 #include <dmlc/thread_local.h>
-#include <vta/runtime.h>
 
+#include "runtime.h"
 #include "../../src/runtime/workspace_pool.h"
 
 

src/runtime.cc → runtime/runtime.cc

@@ -26,15 +26,17 @@
  */
 #include <vta/driver.h>
 #include <vta/hw_spec.h>
-#include <vta/runtime.h>
 #include <dmlc/logging.h>
 #include <tvm/runtime/c_runtime_api.h>
 
+#include <algorithm>
 #include <cassert>
 #include <cstring>
 #include <vector>
 #include <memory>
 
+#include "runtime.h"
+
 namespace vta {
 
 // Avoid bad configurations.

include/vta/runtime.h → runtime/runtime.h

@@ -6,9 +6,9 @@
  * to you under the Apache License, Version 2.0 (the
  * "License"); you may not use this file except in compliance
  * with the License.  You may obtain a copy of the License at
- * 
+ *
  *   http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing,
  * software distributed under the License is distributed on an
  * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
@@ -22,15 +22,15 @@
  * \brief VTA runtime library.
  */
 
-#ifndef VTA_RUNTIME_H_
-#define VTA_RUNTIME_H_
+#ifndef VTA_RUNTIME_RUNTIME_H_
+#define VTA_RUNTIME_RUNTIME_H_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #include <tvm/runtime/c_runtime_api.h>
-#include "driver.h"
+#include <vta/driver.h>
 
 #define VTA_MEMCPY_H2D 1
 #define VTA_MEMCPY_D2H 2
@@ -291,4 +291,4 @@ TVM_DLL void VTASynchronize(VTACommandHandle cmd, uint32_t wait_cycles);
 #ifdef __cplusplus
 }
 #endif
-#endif  // VTA_RUNTIME_H_
+#endif  // VTA_RUNTIME_RUNTIME_H_

tutorials/autotvm/tune_relay_vta.py

@@ -181,7 +181,7 @@ def compile_network(env, target, model, start_pack, stop_pack):
 tracker_host = os.environ.get("TVM_TRACKER_HOST", '0.0.0.0')
 tracker_port = int(os.environ.get("TVM_TRACKER_PORT", 9190))
 
-# Load VTA parameters from the vta/config/vta_config.json file
+# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # This target is used for cross compilation. You can query it by :code:`gcc -v` on your device.

tutorials/frontend/deploy_classification.py

@@ -68,7 +68,7 @@
 # -------------------------------------
 # Execute on CPU vs. VTA, and define the model.
 
-# Load VTA parameters from the vta/config/vta_config.json file
+# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # Set ``device=arm_cpu`` to run inference on the CPU

tutorials/frontend/deploy_detection.py

@@ -111,7 +111,7 @@
 # --------------------------------------
 # Execute on CPU vs. VTA, and define the model.
 
-# Load VTA parameters from the vta/config/vta_config.json file
+# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
 env = vta.get_env()
 # Set ``device=arm_cpu`` to run inference on the CPU
 # or ``device=vta`` to run inference on the FPGA.

tutorials/matrix_multiply.py

@@ -43,7 +43,7 @@
 from tvm.contrib import util
 from vta.testing import simulator
 
-# Load VTA parameters from the vta/config/vta_config.json file
+# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # We read the Pynq RPC host IP address and port number from the OS environment

tutorials/optimize/convolution_opt.py

@@ -47,7 +47,7 @@
 from tvm.contrib import util
 from vta.testing import simulator
 
-# Load VTA parameters from the vta/config/vta_config.json file
+# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # We read the Pynq RPC host IP address and port number from the OS environment

tutorials/optimize/matrix_multiply_opt.py

@@ -46,7 +46,7 @@
 from tvm.contrib import util
 from vta.testing import simulator
 
-# Load VTA parameters from the vta/config/vta_config.json file
+# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
 env = vta.get_env()
 
 # We read the Pynq RPC host IP address and port number from the OS environment

apps/tsim_example/CMakeLists.txt → vta-hw/apps/gemm/CMakeLists.txt

@@ -18,13 +18,13 @@
 cmake_minimum_required(VERSION 3.2)
 project(tsim C CXX)
 
-set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../)
-set(VTA_DIR ${TVM_DIR}/vta)
+set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../../)
+set(VTA_HW_DIR ${TVM_DIR}/3rdparty/vta-hw)
 
 include_directories("${TVM_DIR}/include")
 include_directories("${TVM_DIR}/3rdparty/dlpack/include")
 include_directories("${TVM_DIR}/3rdparty/dmlc-core/include")
-include_directories("${TVM_DIR}/vta/src/dpi")
+include_directories("${VTA_HW_DIR}/src/dpi")
 
 set(CMAKE_C_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden")
 set(CMAKE_CXX_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden -std=c++11")
@@ -35,11 +35,11 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND
 endif()
 
 file(GLOB TSIM_SW_SRC src/driver.cc)
-list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/vmem/virtual_memory.cc)
-list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/dpi/module.cc)
+list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/vmem/virtual_memory.cc)
+list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/dpi/module.cc)
 
 add_library(sw SHARED ${TSIM_SW_SRC})
-target_include_directories(sw PRIVATE ${VTA_DIR}/include ${VTA_DIR}/src)
+target_include_directories(sw PRIVATE ${VTA_HW_DIR}/include ${VTA_HW_DIR}/src)
 
 if(APPLE)
   set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")

apps/gemm/Makefile → vta-hw/apps/gemm/Makefile

@@ -15,15 +15,15 @@
 # specific language governing permissions and limitations
 # under the License.
 
-export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
+export PYTHONPATH:=$(abspath .)/python:$(PYTHONPATH)
+export PYTHONPATH:=$(abspath .)/../../../../python:$(PYTHONPATH)
 
 BUILD_NAME = build
 build_dir = $(abspath .)/$(BUILD_NAME)
 
-default: chisel driver
-	python3 tests/python/chisel_accel.py serial
+default: chisel driver serial parallel
 
-serial:  
+serial:
 	python3 tests/python/chisel_accel.py serial
 
 parallel:

apps/gemm/README.md → vta-hw/apps/gemm/README.md

@@ -15,9 +15,9 @@
 <!--- specific language governing permissions and limitations -->
 <!--- under the License. -->
 
-VTA TSIM Application 
+VTA TSIM Application
 ======================
-Prior to this application, please take a look at `<tvm-root>/vta/apps/tsim_example` for installation
+Prior to this application, please take a look at `<tvm-root>/vta/vta-hw/apps/tsim_example` for installation
 This is an application that performs Bit Serial Multiplication for GEMM utilizing TSIM.
 
 **Bit Serial Multiplication for GEMM:**
@@ -28,23 +28,23 @@ We approach this operation with slicing and shifting, like how basic multiplicat
 We can sufficiently reduce the cycles required to perform a gemm given that the data bit width is small. This GEMM application uses TSIM for future accerlerator prototypes.
 
 * Test Chisel3 backend with bit serial GEMM
-    * Go to `<tvm-root>/vta/apps/gemm`
+    * Go to `<tvm-root>/vta/vta-hw/apps/gemm`
     * Run `make`
 
-* If you have already compiled chisel backend (i.e. ran `make`) 
+* If you have already compiled chisel backend (i.e. ran `make`)
     * Bit Serial test with another input set, run `make serial`
     * Bit parallel test with another input set, run `make parallel`
 
 * Some steps for creating your own custom TSIM application
-    * Go to `<tvm-root>/vta/apps/gemm`
+    * Go to `<tvm-root>/vta/vta-hw/apps/gemm`
     * Create custom circuit within `./hardware/chisel/src/scala.main/accel/Compute.scala`
     * Map the according Registers in `./hardware/chisel/src/scala.main/accel/RegFile.scala`
     * Create your test script
     * Map the registers in `./src/driver.cc` and link it with both `RegFile.scala` and the test script
-    * Understanding of `<tvm-root>/vta/apps/tsim_example`, which performs add by one to a vector, is highly encouraged to create a more complex application
+    * Understanding of `<tvm-root>/vta/vta-hw/apps/tsim_example`, which performs add by one to a vector, is highly encouraged to create a more complex application
 
 * Some pointers
-    * Chisel3 tests in `<tvm-root>/vta/apps/gemm/tests/python`
-    * Chisel3 accelerator backend `<tvm-root>/vta/apps/gemm/hardware/chisel`
-    * Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/apps/gemm/src/driver.cc`
-    * Software Python driver (frontend) that handles the accelerator `<tvm-root>/vta/apps/gemm/python/accel`
+    * Chisel3 tests in `<tvm-root>/vta/vta-hw/apps/gemm/tests/python`
+    * Chisel3 accelerator backend `<tvm-root>/vta/vta-hw/apps/gemm/hardware/chisel`
+    * Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/vta-hw/apps/gemm/src/driver.cc`
+    * Software Python driver (frontend) that handles the accelerator `<tvm-root>vtay/vta-hw/apps/gemm/python/accel`

apps/gemm/hardware/chisel/Makefile → vta-hw/apps/gemm/hardware/chisel/Makefile

@@ -38,7 +38,7 @@ USE_TRACE = 1
 LIBNAME = libhw
 
 vta_dir = $(abspath ../../../../)
-tvm_dir = $(abspath ../../../../../)
+tvm_dir = $(abspath ../../../../../../)
 build_dir = $(abspath .)/$(BUILD_NAME)
 verilator_build_dir = $(build_dir)/verilator
 chisel_build_dir = $(build_dir)/chisel

apps/gemm/hardware/chisel/project/build.properties → vta-hw/apps/gemm/hardware/chisel/project/build.properties

@@ -17,4 +17,4 @@
  * under the License.
  */
 
-sbt.version = 1.1.1
+sbt.version = 1.3.2

apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala → vta-hw/apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala

@@ -89,7 +89,7 @@ class Compute(implicit config: AccelConfig) extends Module {
     is (sReadAData) {
       when (io.mem.rd.valid) {
         state := sReadADone
-      }   
+      }
     }
     is (sReadADone) {
       when (cntwgt === (length * length) - 1.U) {
@@ -180,8 +180,8 @@ class Compute(implicit config: AccelConfig) extends Module {
   }
 
   io.mem.rd.ready := state === sReadAData | state === sReadBData
-  mvc.io.inp.data.valid := state === sInpDone // 2 inputs have been processed 
-  mvc.io.wgt.data.valid := state === sInpDone // 2 inputs have been processed 
+  mvc.io.inp.data.valid := state === sInpDone // 2 inputs have been processed
+  mvc.io.wgt.data.valid := state === sInpDone // 2 inputs have been processed
 
   mvc.io.wgt.data.bits <> reg1
   mvc.io.inp.data.bits <> reg2
@@ -198,7 +198,7 @@ class Compute(implicit config: AccelConfig) extends Module {
   accum.io.valid := mvc.io.acc_o.data.valid
 
   // write
-  io.mem.wr.valid := state === sWriteData 
+  io.mem.wr.valid := state === sWriteData
   io.mem.wr.bits := accum.io.sum(cntout)
 
   // count read/write

apps/gemm/CMakeLists.txt → vta-hw/apps/tsim_example/CMakeLists.txt

@@ -18,13 +18,13 @@
 cmake_minimum_required(VERSION 3.2)
 project(tsim C CXX)
 
-set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../)
-set(VTA_DIR ${TVM_DIR}/vta)
+set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../../)
+set(VTA_HW_DIR ${TVM_DIR}/vta/vta-hw)
 
 include_directories("${TVM_DIR}/include")
 include_directories("${TVM_DIR}/3rdparty/dlpack/include")
 include_directories("${TVM_DIR}/3rdparty/dmlc-core/include")
-include_directories("${TVM_DIR}/vta/src/dpi")
+include_directories("${VTA_HW_DIR}/src/dpi")
 
 set(CMAKE_C_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden")
 set(CMAKE_CXX_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden -std=c++11")
@@ -35,11 +35,11 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND
 endif()
 
 file(GLOB TSIM_SW_SRC src/driver.cc)
-list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/vmem/virtual_memory.cc)
-list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/dpi/module.cc)
+list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/vmem/virtual_memory.cc)
+list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/dpi/module.cc)
 
 add_library(sw SHARED ${TSIM_SW_SRC})
-target_include_directories(sw PRIVATE ${VTA_DIR}/include ${VTA_DIR}/src)
+target_include_directories(sw PRIVATE ${VTA_HW_DIR}/include ${VTA_HW_DIR}/src)
 
 if(APPLE)
   set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")

apps/tsim_example/Makefile → vta-hw/apps/tsim_example/Makefile

@@ -20,7 +20,9 @@ export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
 BUILD_NAME = build
 build_dir = $(abspath .)/$(BUILD_NAME)
 
-default: verilog driver
+default: run_verilog
+
+run_verilog: verilog driver
 	python3 tests/python/verilog_accel.py
 
 run_chisel: chisel driver