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JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B (dotnet#9…
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…7129)

* Added SVE_JD_4A format

* Added SVE_JD_4B format

* Added SVE_JJ_4A format, added more formats but they are commented out for now

* Added SVE_JJ_4A_B format

* Revert minor change

* Minor cleanup

* Cleanup. Fixed a few formats. Introduced new INS_OPTS_SCALABLE options for UXTW and SXTW

* Added SVE_JJ_4A_C format

* Added SVE_JJ_4A_D format

* Added SVE_JK_4A and SVE_JK_4A_B formats

* Added SVE_JN_3A format

* Added SVE_JN_3B format

* Some comments

* Feedback

* Feedback

* fix build

* Formatting
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@TIHan @tmds
TIHan authored and tmds committed Jan 23, 2024
1 parent 688e3cd commit bf3f181
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104 changes: 104 additions & 0 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5881,6 +5881,110 @@ void CodeGen::genArm64EmitterUnitTestsSve()
theEmitter->emitIns_R_R_R_I(INS_sve_st4w, EA_SCALABLE, REG_V31, REG_P1, REG_R5, 28,
INS_OPTS_SCALABLE_S); // ST4W {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>{,
// #<imm>, MUL VL}]

// IF_SVE_JD_4A
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P1, REG_R2, REG_R0,
INS_OPTS_SCALABLE_B); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P5, REG_R6, REG_R2,
INS_OPTS_SCALABLE_H); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V6, REG_P5, REG_R7, REG_R4,
INS_OPTS_SCALABLE_S); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P0, REG_R1, REG_R2,
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P6, REG_R1, REG_R2, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_LSL_N); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V1, REG_P2, REG_R3, REG_R4, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_LSL_N); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V3, REG_P2, REG_R4, REG_R0, INS_OPTS_SCALABLE_D,
INS_SCALABLE_OPTS_LSL_N); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]

// IF_SVE_JD_4B
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P1, REG_R2, REG_R3, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_LSL_N); // ST1W {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V2, REG_P3, REG_R4, REG_R5, INS_OPTS_SCALABLE_D,
INS_SCALABLE_OPTS_LSL_N); // ST1W {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

// IF_SVE_JJ_4A
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V0, REG_P1, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V0, REG_P1, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V3, REG_P1, REG_R5, REG_V4, INS_OPTS_SCALABLE_S_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V3, REG_P1, REG_R5, REG_V4, INS_OPTS_SCALABLE_S_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P3, REG_R1, REG_V2, INS_OPTS_SCALABLE_S_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P3, REG_R1, REG_V2, INS_OPTS_SCALABLE_S_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]

// IF_SVE_JJ_4A_B
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P1, REG_R2, REG_V5,
INS_OPTS_SCALABLE_D_UXTW); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P1, REG_R2, REG_V5,
INS_OPTS_SCALABLE_D_SXTW); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V2, REG_P3, REG_R1, REG_V4, INS_OPTS_SCALABLE_D_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V2, REG_P3, REG_R1, REG_V4, INS_OPTS_SCALABLE_D_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V1, REG_P4, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V1, REG_P4, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]

// IF_SVE_JJ_4A_C
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V1, REG_P5, REG_R1, REG_V3,
INS_OPTS_SCALABLE_D_UXTW); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V1, REG_P5, REG_R1, REG_V3,
INS_OPTS_SCALABLE_D_SXTW); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P2, REG_R3, REG_V4,
INS_OPTS_SCALABLE_D_UXTW); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P2, REG_R3, REG_V4,
INS_OPTS_SCALABLE_D_SXTW); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]

// IF_SVE_JJ_4A_D
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V7, REG_P5, REG_R4, REG_V1,
INS_OPTS_SCALABLE_S_UXTW); // ST1H {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V7, REG_P5, REG_R4, REG_V1,
INS_OPTS_SCALABLE_S_SXTW); // ST1H {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V1, REG_P2, REG_R3, REG_V2,
INS_OPTS_SCALABLE_S_UXTW); // ST1W {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V1, REG_P2, REG_R3, REG_V2,
INS_OPTS_SCALABLE_S_SXTW); // ST1W {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]

// IF_SVE_JK_4A
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P2, REG_R0, REG_V1,
INS_OPTS_SCALABLE_D_UXTW); // ST1B {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P2, REG_R0, REG_V1,
INS_OPTS_SCALABLE_D_SXTW); // ST1B {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]

// IF_SVE_JK_4A_B
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P4, REG_R3, REG_V0,
INS_OPTS_SCALABLE_S_UXTW); // ST1B {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P4, REG_R3, REG_V0,
INS_OPTS_SCALABLE_S_SXTW); // ST1B {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]

// IF_SVE_JN_3A
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V3, REG_P2, REG_R1, 5,
INS_OPTS_SCALABLE_B); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V3, REG_P2, REG_R1, 4,
INS_OPTS_SCALABLE_H); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V0, REG_P3, REG_R4, 3,
INS_OPTS_SCALABLE_H); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V3, REG_P2, REG_R1, 2,
INS_OPTS_SCALABLE_S); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V0, REG_P3, REG_R4, 1,
INS_OPTS_SCALABLE_S); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V3, REG_P2, REG_R1, 0,
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V0, REG_P3, REG_R4, -2,
INS_OPTS_SCALABLE_D); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

// IF_SVE_JN_3B
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V2, REG_P1, REG_R3, 5,
INS_OPTS_SCALABLE_S); // ST1W {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V2, REG_P1, REG_R3, 1,
INS_OPTS_SCALABLE_D); // ST1W {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
}

#endif // defined(TARGET_ARM64) && defined(DEBUG)
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