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/* | ||
* Licensed to the Apache Software Foundation (ASF) under one | ||
* or more contributor license agreements. See the NOTICE file | ||
* distributed with this work for additional information | ||
* regarding copyright ownership. The ASF licenses this file | ||
* to you under the Apache License, Version 2.0 (the | ||
* "License"); you may not use this file except in compliance | ||
* with the License. You may obtain a copy of the License at | ||
* | ||
* http://www.apache.org/licenses/LICENSE-2.0 | ||
* | ||
* Unless required by applicable law or agreed to in writing, | ||
* software distributed under the License is distributed on an | ||
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY | ||
* KIND, either express or implied. See the License for the | ||
* specific language governing permissions and limitations | ||
* under the License. | ||
*/ | ||
#include "./utils.h" | ||
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namespace tvm { | ||
namespace tir { | ||
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Stmt RealizeInitBlock(const Stmt& init, const Array<IterVar>& iter_vars) { | ||
std::vector<PrimExpr> conditions; | ||
for (const IterVar& var : iter_vars) { | ||
if (var->iter_type == IterVarType::kCommReduce) { | ||
conditions.push_back(equal(var->var, var->dom->min)); | ||
} | ||
} | ||
int n = conditions.size(); | ||
// Handle the case where there is no condition | ||
if (n == 0) { | ||
return init; | ||
} | ||
// Concate the conditions with logical and (&&) | ||
PrimExpr cond = conditions[0]; | ||
for (int i = 1; i < n; ++i) { | ||
cond = logical_and(cond, conditions[i]); | ||
} | ||
return IfThenElse(cond, init); | ||
} | ||
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} // namespace tir | ||
} // namespace tvm |
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/* | ||
* Licensed to the Apache Software Foundation (ASF) under one | ||
* or more contributor license agreements. See the NOTICE file | ||
* distributed with this work for additional information | ||
* regarding copyright ownership. The ASF licenses this file | ||
* to you under the Apache License, Version 2.0 (the | ||
* "License"); you may not use this file except in compliance | ||
* with the License. You may obtain a copy of the License at | ||
* | ||
* http://www.apache.org/licenses/LICENSE-2.0 | ||
* | ||
* Unless required by applicable law or agreed to in writing, | ||
* software distributed under the License is distributed on an | ||
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY | ||
* KIND, either express or implied. See the License for the | ||
* specific language governing permissions and limitations | ||
* under the License. | ||
*/ | ||
#ifndef TVM_TIR_SCHEDULE_TRANSFORM_H_ | ||
#define TVM_TIR_SCHEDULE_TRANSFORM_H_ | ||
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#include <tvm/tir/stmt.h> | ||
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#include <unordered_set> | ||
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namespace tvm { | ||
namespace tir { | ||
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/*! | ||
* \brief Transform the init block into actual computation | ||
* \param init The init block | ||
* \param iter_vars The block variables | ||
* \return The actual computation | ||
*/ | ||
Stmt RealizeInitBlock(const Stmt& init, const Array<IterVar>& iter_vars); | ||
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} // namespace tir | ||
} // namespace tvm | ||
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#endif // TVM_TIR_SCHEDULE_TRANSFORM_H_ |
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