Initial gateware code for VGA capture #215
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mithro
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| def do_simulation(self, selfp): | ||
| print ("cycle: {cycle} , hsync: {hsync}, vsync: {vsync}, de: {de}, r: {r}, g: {g}, b: {b}".format( |
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Can you please fix the wrapping here.
Something like;
print("cycle: {cycle} , hsync: {hsync}, vsync: {vsync}, de: {de}, r: {r}, g: {g}, b: {b}".format(
cycle = selfp.simulator.cycle_counter,
hsync = selfp.hsync,
vsync = selfp.vsync,
de = selfp.de,
r = selfp.r,
g = selfp.g,
b = selfp.b,
))
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Hi @rohit91, Generally things are looking pretty good but there are some small formatting issues. Can you please do the following things;
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@enjoy-digital Can you take a close look at the migen code? |
| * www.analog.com/media/en/technical-documentation/data-sheets/AD9984A.pdf | ||
| * | ||
| * Code below is for AD9984A based VGA capturing for HDMI2USB using VGA | ||
| * Expansion Board for Atlys(https://github.com/timvideos/HDMI2USB-vmodvga) |
rohitk-singh
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rohitk-singh
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Starting afresh. Changes:
@mithro Can you look at this and see if it can be merged or not. pep8 checks are ok (only visual indentation warnings and few >79 line-length warnings). I have incorporated all of @enjoy-digital's suggestions he had after his review. This gateware code is all that is necessary for vga capture. I'll be creating separate pull requests each for firmware and for target. |
| self.counterY.eq(0), | ||
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| # VGA Scan Timing Values used below for 1024x768@60Hz |
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Can you add a TODO to make this configurable / controllable?
Files:
new file: gateware/vga/__init__.py
new file: gateware/vga/analysis.py
new file: gateware/vga/datacapture.py
__init__.py:
Implements VGAIn module which instantiates submodules
Datacapture, FrameExtrantion and DMA, and connects them
analysis.py:
Implements FrameExtraction module, which is reponsible
for sof(start of frame) detection, color space conversion,
framing(packing) and also uses async fifo to move data
from VGA pixel clock domain to sys_clk domain
datacapture.py:
Implements DataCapture module which is responsible for
capturing pixel data at proper time, depending on HSYNC
and VSYNC signals
Currently only supports 1024x768@60Hz resolution capture
VGAIn modules gives VGA capture functionality to atlys. Also, we are now inheriting BaseSoC class directly instead of MinoSoC
Added to _io_vccb2_3v3 list because currently VGA signals are driven at 3.3V. This is going to change and become configurable later.
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Changes:
gateware/vgaatlys_vga.pytarget for vga capturead9984a.candvga_in.cDoesn't have to merged compulsorily. If any suggestions or refactoring/restructuring ideas are there, they are welcome. Any comments also welcome.
Have to add rest of the firmware code for capture to work. There are some conflicts with the code, so haven't committed them yet. Looking into them right now