Rename CpuInterface to PipeCon

README.md

@@ -68,6 +68,17 @@ class PipeConIO(private val addrWidth: Int) extends Bundle {
 }
 ```
 
+```PipeCon``` itself is an abstract class, just containing  the interface:
+
+```scala
+abstract class PipeCon(addrWidth: Int) extends Module {
+  val io = IO(new Bundle {
+    val cpuPort = new PipeConIO(addrWidth)
+  })
+  val cp = io.cpuPort
+}
+```
+
 The main rules define PipeCon:
 
  * There are two transactions: read and write
@@ -116,6 +127,22 @@ protocol for accessing IO devices (OCPcore). Memory is connected via a burst int
 The Patmos Handbook gives a detailed description of the
 used OCP interfaces.
 
+#### Ready/Valid Interface
+
+For IO devices with a ready/valid interface (Chisel ```Decoupled```) we
+provide a standard mapping for the ```PipeCon```, the ```PipeConRV```:
+
+ * CPU interface to two ready/valid channels (one for transmit/tx, one for receive/rx).
+ * IO mapping as in the classic PC serial port (UART)
+ * 0: status (control): bit 0 tx ready, bit 1 rx data available
+ * 1: write into txd and read from rxd
+
+Additionally, for the S4NOC we provide following port:
+
+ * 2: write receiver, read sender (S4NOC specific)
+
+
+
 ### S4NOC
 
 The network interface and the S4NOC are written in Chisel and the
@@ -165,7 +192,7 @@ To analyze memory issues (e.g., increase the heap size with Xmx) use a ```.sbtop
 
 ## TODO
 
- * [x] Use and document the PipeCon, direction from master
+ * [x] Use and document the PipeCon, direction from slave
    * Or stick to the CpuInterface as it is and rename it
  * [ ] Wrapper for OCP (in Patmos)
  * [ ] Integrate a simple multicore device with T-CREST

src/main/scala/s4noc/S4NoCTop.scala

@@ -19,7 +19,7 @@ class S4NoCTop(conf: Config) extends Module  {
 
   val s4noc = Module(new S4NoC(conf))
   for (i <- 0 until conf.n) {
-    val ci = Module(new CpuInterfaceRV(conf.width, Entry(UInt(conf.width.W)), true))
+    val ci = Module(new PipeConRV(conf.width, Entry(UInt(conf.width.W)), true))
     s4noc.io.networkPort(i) <> ci.rv
     io.cpuPorts(i) <> ci.io.cpuPort
   }

src/main/scala/soc/HardwareLock.scala

@@ -13,7 +13,7 @@ import chisel3._
   *
   * Could be extended to a multicore lock.
   */
-class HardwareLock() extends CpuInterface(0) {
+class HardwareLock() extends PipeCon(0) {
 
   val lockReg = RegInit(false.B)
   val ackReg = RegInit(false.B)

src/main/scala/soc/HelloDevice.scala

@@ -9,7 +9,7 @@ import chisel3._
   *
   * @param coreId
   */
-class HelloDevice(coreId: Int) extends CpuInterface(2) {
+class HelloDevice(coreId: Int) extends PipeCon(2) {
 
   // TODO: following five lines are duplicated in CpuInterfaceRV, back to CpuInterface?
   val addrReg = RegInit(0.U(2.W))

src/main/scala/soc/CpuInterface.scala → src/main/scala/soc/PipeCon.scala

@@ -6,7 +6,7 @@ import chisel3._
   * Just a CPU interface, without any additional connection.
   *
   */
-abstract class CpuInterface(addrWidth: Int) extends Module {
+abstract class PipeCon(addrWidth: Int) extends Module {
   val io = IO(new Bundle {
     val cpuPort = new PipeConIO(addrWidth)
   })

src/main/scala/soc/CpuInterfaceRV.scala → src/main/scala/soc/PipeConRV.scala

@@ -13,7 +13,7 @@ import s4noc.Entry
   * TODO: compare with Chisel book version
   * TODO: make it generic and do a subtype for s4noc
   */
-class CpuInterfaceRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc: Boolean = false ) extends CpuInterface(addrWidth) {
+class PipeConRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc: Boolean = false ) extends PipeCon(addrWidth) {
 
   val rv = IO(new ReadyValidChannelsIO(dt))
 

src/test/scala/soc/CpuInterfaceRVTest.scala → src/test/scala/soc/PipeConRVTest.scala

@@ -7,11 +7,11 @@ import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
 import s4noc.Entry
 
-class CpuInterfaceRVTest extends AnyFlatSpec with ChiselScalatestTester {
+class PipeConRVTest extends AnyFlatSpec with ChiselScalatestTester {
   behavior of "The CpuInterfaceRV"
 
   it should "do something" in {
-    test(new CpuInterfaceRV(4, UInt(32.W))) {
+    test(new PipeConRV(4, UInt(32.W))) {
       d => {
 
         def step() = d.clock.step()
@@ -58,8 +58,8 @@ class CpuInterfaceRVTest extends AnyFlatSpec with ChiselScalatestTester {
   }
 
   // Connect a CPU interface to a FIFO
-  class MyModule() extends CpuInterface(4) {
-    val cpif = Module(new CpuInterfaceRV(4, UInt(32.W)))
+  class MyModule() extends PipeCon(4) {
+    val cpif = Module(new PipeConRV(4, UInt(32.W)))
     val fifo = Module(new BubbleFifo(UInt(32.W), 4))
     io.cpuPort <> cpif.io.cpuPort
     cpif.tx <> fifo.io.enq
@@ -95,8 +95,8 @@ class CpuInterfaceRVTest extends AnyFlatSpec with ChiselScalatestTester {
       val cpA = new PipeConIO(4)
       val cpB = new PipeConIO(4)
     })
-    val cpifA = Module(new CpuInterfaceRV(4, UInt(32.W)))
-    val cpifB = Module(new CpuInterfaceRV(4, UInt(32.W)))
+    val cpifA = Module(new PipeConRV(4, UInt(32.W)))
+    val cpifB = Module(new PipeConRV(4, UInt(32.W)))
     val fifoA = Module(new MemFifo(UInt(32.W), 4))
     val fifoB = Module(new MemFifo(UInt(32.W), 4))
 
@@ -176,23 +176,21 @@ class CpuInterfaceRVTest extends AnyFlatSpec with ChiselScalatestTester {
   }
 
   // Connect a CPU interface to a FIFO with Entry
-  class MyModule3() extends CpuInterface(4) {
-    val cpif = Module(new CpuInterfaceRV(4, Entry(UInt(32.W)), true))
+  class MyModule3() extends PipeCon(4) {
+    val cpif = Module(new PipeConRV(4, Entry(UInt(32.W)), true))
     val fifo = Module(new BubbleFifo(Entry(UInt(32.W)), 4))
-    io.cpuPort <> cpif.io.cpuPort
+    cp <> cpif.io.cpuPort
     cpif.tx <> fifo.io.enq
     cpif.rx <> fifo.io.deq
   }
 
   it should "do work with a S4NOC Entry" in {
     test(new MyModule3()).withAnnotations(Seq(WriteVcdAnnotation)) {
       d => {
-
-        val cp = d.io.cpuPort
         val helper = new MemoryMappedIOHelper(d.cp, d.clock)
 
         d.clock.step()
-        cp.ack.expect(false.B)
+        d.cp.ack.expect(false.B)
         helper.write(2, 0x12)
         helper.write(1, 0x34)
         // should come back on the RX port