update project for custom DTM with Intel JTAG

stnolting · Aug 30, 2023 · e1324c7 · e1324c7
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diff --git a/quartus/on-chip-debugger-intel/README.md b/quartus/on-chip-debugger-intel/README.md
@@ -41,8 +41,8 @@ configuration and entity details.
 ### FPGA Utilization
 
 ```
-Total logic elements                    3,786 / 15,408 ( 25 % )
-Total registers                         1,835 / 17,056 ( 11 % )
+Total logic elements                    3,791 / 15,408 ( 25 % )
+Total registers                         1,750 / 17,056 ( 11 % )
 Total LABs                              291 / 963 ( 30 % )
 Virtual pins                            0
 I/O pins                                10 / 344 ( 3 % )