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Added option byte address for L4Rx devices #1254
Added option byte address for L4Rx devices #1254
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Hi! In L496x_L4A6x.chip, |
Oh, no, |
Almost all other chip files have a comment referencing a C constant next to the stlink/config/chips/L496x_L4A6x.chip Line 12 in 951859c
I don’t know if/when it is necessary, hopefully someone else will explain it. |
@bauen1 @gszy It should always be present in the chip-id files and if option byte use is implemented in the code as well for the respective mcu type the related memory address from the reference manual needs to be present in the chip-id file. Otherwise 0x0 is set. So please only update this setting if the interaction with option bytes is also implemented in the codebase. As far as I can see this is currently not the case here. |
@Nightwalker-87 What code would be missing ? I don't have a STM32L496 / STM32L4R5 available to test right now, but looking at the code, there is already |
One would have to check especially |
@Nightwalker-87 The method The L4 / L4P have the same flash type and the same magic dance for updating the option bytes. I've also just tested it again by disabling / enabling the ST bootloader, and it works correctly. |
@bauen1 As there appears to be no difference between L4 and L4P in the behaviour on writing option bytes, it shall be fine to preserve the method What device was used for testing? |
@Nightwalker-87 It was tested on a nucleo development board (https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) and an in-house developed board with a stm32l4r5zi . |
ok. It would be good though if we had at least one further L4/L4P-device of different type tested successfully. |
@Nightwalker-87 You mean another L4P device ? Because nothing changed for the L4 devices, though I could test that with an STM32L496ZI |
The location of the option bytes is the same as for the STM32L496ZG.It is different due to different flash sizes.
It was tested to work by disabling the ST Bootloader on various self build boards.