initial l5 support

config/chips/L5x2.chip

@@ -0,0 +1,14 @@
+# Chip-ID file for STM32L5x2 device
+#
+dev_type STM32L5x2
+ref_manual_id 0438
+chip_id 0x472                // RM0438, pg. 2157
+flash_type L5_U5             // ???
+flash_size_reg 0x0bfa05e0    // RM0438, pg. 2166
+flash_pagesize 0x1000        // 4 KB - RM0438, pg. 178
+sram_size 0x40000            // 256 KB - RM0438, pg. 94
+bootrom_base 0x0bf90000      // RM0438, pg. 98/179
+bootrom_size 0x8000          // 32 KB - RM0438, pg. 179
+option_base 0x0              // ???
+option_size 0x0              // ???
+flags none                   // ???

inc/stm32.h

@@ -117,6 +117,7 @@ enum stm32_chipids {
     STM32_CHIPID_G4_CAT3          = 0x469,
     STM32_CHIPID_L4Rx             = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */
     STM32_CHIPID_L4PX             = 0x471, /* RM0432, p.2247 */
+    STM32_CHIPID_L5x2             = 0x472, /* RM0438, p.2157 */
     STM32_CHIPID_G4_CAT4          = 0x479,
     STM32_CHIPID_H7Ax             = 0x480, /* RM0455, p.2863 */
     STM32_CHIPID_H72x             = 0x483, /* RM0468, p.3199 */
@@ -193,6 +194,11 @@ enum stm32_chipids {
 #define STM32L0_RCC_AHBENR 0x40021030
 #define STM32L0_RCC_DMAEN 0x00000001 // DMAEN
 
+// RM0438, pg. 91,377
+#define STM32L5_RCC_AHB1ENR 0x40021048
+// RM0438, pg. 378
+#define STM32L5_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
+
 #define STM32L1_RCC_AHBENR 0x4002381C
 #define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN
 
@@ -202,4 +208,8 @@ enum stm32_chipids {
 #define STM32WB_RCC_AHB1ENR 0x58000048
 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
 
+// RM0438, pg. 93,324
+#define STM32L5_PWR_CR1 0x40007000
+#define STM32L5_PWR_CR1_VOS 8
+
 #endif // STM32_H

inc/stm32flash.h

@@ -73,6 +73,7 @@
 #define FLASH_L1_PROG 3
 
 // Flash registers common to STM32G0 and STM32G4 series.
+// RM0440, pg 146
 #define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000)
 #define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00)
 #define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08)
@@ -207,6 +208,46 @@
 
 #define STM32L4_FLASH_OPTR_DUALBANK 21
 
+// Flash registers common to STM32L5 series
+// RM0438, pg. 241
+#define STM32L5_FLASH_REGS_ADDR ((uint32_t)0x40022000)
+#define STM32L5_FLASH_ACR (STM32L5_FLASH_REGS_ADDR + 0x00)
+#define STM32L5_FLASH_NSKEYR (STM32L5_FLASH_REGS_ADDR + 0x08)
+#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASH_REGS_ADDR + 0x10)
+#define STM32L5_FLASH_NSSR (STM32L5_FLASH_REGS_ADDR + 0x20)
+#define STM32L5_FLASH_NSCR (STM32L5_FLASH_REGS_ADDR + 0x28)
+#define STM32L5_FLASH_ECCR (STM32L5_FLASH_REGS_ADDR + 0x30)
+#define STM32L5_FLASH_OPTR (STM32L5_FLASH_REGS_ADDR + 0x40)
+
+// FLASH_NSCR
+// RM0438, pg. 242
+#define STM32L5_FLASH_NSCR_NSPG 0        /* Program */
+#define STM32L5_FLASH_NSCR_NSPER 1       /* Page erase */
+#define STM32L5_FLASH_NSCR_NSMER1 2      /* Bank 1 erase */
+#define STM32L5_FLASH_NSCR_NSPNB 3       /* Page number (7 bits) */
+#define STM32L5_FLASH_NSCR_NSBKER 11     /* Bank select for page erase */
+#define STM32L5_FLASH_NSCR_NSMER2 15     /* Bank 2 erase */
+#define STM32L5_FLASH_NSCR_NSSTRT 16     /* Start command */
+#define STM32L5_FLASH_NSCR_NSOPTSTRT 17  /* Start writing option bytes */
+#define STM32L5_FLASH_NSCR_NSEOPIE 24
+#define STM32L5_FLASH_NSCR_NSERRIE 25
+#define STM32L5_FLASH_NSCR_OBL_LAUNCH 27 /* Option bytes reload */
+#define STM32L5_FLASH_NSCR_OPTLOCK 30    /* Lock option bytes */
+#define STM32L5_FLASH_NSCR_NSLOCK 31     /* Lock control register */
+
+// FLASH_NSSR
+// RM0438, pg. 241
+#define STM32L5_FLASH_NSSR_NSEOP 0       /* End of Operation */
+#define STM32L5_FLASH_NSSR_NSOPERR 1
+#define STM32L5_FLASH_NSSR_NSPROGERR 3
+#define STM32L5_FLASH_NSSR_NSWRPERR 4
+#define STM32L5_FLASH_NSSR_NSPGAERR 5
+#define STM32L5_FLASH_NSSR_NSSIZERR 6
+#define STM32L5_FLASH_NSSR_NSPGSERR 7
+#define STM32L5_FLASH_NSSR_OPTWERR 12
+#define STM32L5_FLASH_NSSR_BSY 16        /* Busy */
+#define STM32L5_FLASH_NSSR_ERROR_MASK (0x20fa)
+
 // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf
 #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
 

src/common_flash.c

@@ -39,6 +39,8 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) {
     reg = FLASH_F7_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     reg = STM32L4_FLASH_CR;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    reg = STM32L5_FLASH_NSCR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     reg = STM32Gx_FLASH_CR;
@@ -81,6 +83,9 @@ void lock_flash(stlink_t *sl) {
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     cr_reg = STM32L4_FLASH_CR;
     cr_lock_shift = STM32L4_FLASH_CR_LOCK;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
+    cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
@@ -125,6 +130,8 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) {
     sr_reg = FLASH_F7_SR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     sr_reg = STM32L4_FLASH_SR;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    sr_reg = STM32L5_FLASH_NSSR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     sr_reg = STM32Gx_FLASH_SR;
@@ -165,6 +172,9 @@ void clear_flash_error(stlink_t *sl) {
   case STM32_FLASH_TYPE_L4_L4P:
     write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK);
     break;
+  case STM32_FLASH_TYPE_L5_U5:
+    write_flash_sr(sl, BANK_1, STM32L5_FLASH_NSSR_ERROR_MASK);
+    break;
   case STM32_FLASH_TYPE_H7:
     write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK);
     if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) {
@@ -193,6 +203,8 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) {
     sr_reg = FLASH_F7_SR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     sr_reg = STM32L4_FLASH_SR;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    sr_reg = STM32L5_FLASH_NSSR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     sr_reg = STM32Gx_FLASH_SR;
@@ -223,6 +235,8 @@ unsigned int is_flash_busy(stlink_t *sl) {
     sr_busy_shift = FLASH_F7_SR_BSY;
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     sr_busy_shift = STM32L4_FLASH_SR_BSY;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    sr_busy_shift = STM32L5_FLASH_NSSR_BSY;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     sr_busy_shift = STM32Gx_FLASH_SR_BSY;
@@ -302,6 +316,12 @@ int check_flash_error(stlink_t *sl) {
     PROGERR = (1 << STM32L4_FLASH_SR_PROGERR);
     PGAERR = (1 << STM32L4_FLASH_SR_PGAERR);
     break;
+  case STM32_FLASH_TYPE_L5_U5:
+    res = read_flash_sr(sl, BANK_1) & STM32L5_FLASH_NSSR_ERROR_MASK;
+    WRPERR = (1 << STM32L5_FLASH_NSSR_NSWRPERR);
+    PROGERR = (1 << STM32L5_FLASH_NSSR_NSPROGERR);
+    PGAERR = (1 << STM32L5_FLASH_NSSR_NSPGAERR);
+    break;
   case STM32_FLASH_TYPE_H7:
     res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK;
     if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) {
@@ -362,6 +382,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) {
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     cr_reg = STM32L4_FLASH_CR;
     cr_lock_shift = STM32L4_FLASH_CR_LOCK;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
+    cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
@@ -405,6 +428,17 @@ static void unlock_flash(stlink_t *sl) {
     flash_key2 = FLASH_L0_PEKEY2;
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     key_reg = STM32L4_FLASH_KEYR;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    // Set voltage scaling to range 0 to perform flash operations
+    // RM0438 pg. 183
+    uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS);
+    uint32_t val;
+    stlink_read_debug32(sl, STM32L5_PWR_CR1, &val);
+    if ((val & mask) > (1 << STM32L5_PWR_CR1_VOS)) {
+      val &= ~mask;
+      stlink_write_debug32(sl, STM32L5_PWR_CR1, val);
+    }
+    key_reg = STM32L5_FLASH_NSKEYR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     key_reg = STM32Gx_FLASH_KEYR;
@@ -471,6 +505,10 @@ int lock_flash_option(stlink_t *sl) {
     optcr_reg = STM32L4_FLASH_CR;
     optlock_shift = STM32L4_FLASH_CR_OPTLOCK;
     break;
+  case STM32_FLASH_TYPE_L5_U5:
+    optcr_reg = STM32L5_FLASH_NSCR;
+    optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK;
+    break;
   case STM32_FLASH_TYPE_G0:
   case STM32_FLASH_TYPE_G4:
     optcr_reg = STM32Gx_FLASH_CR;
@@ -544,6 +582,10 @@ static bool is_flash_option_locked(stlink_t *sl) {
     optcr_reg = STM32L4_FLASH_CR;
     optlock_shift = STM32L4_FLASH_CR_OPTLOCK;
     break;
+  case STM32_FLASH_TYPE_L5_U5:
+    optcr_reg = STM32L5_FLASH_NSCR;
+    optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK;
+    break;
   case STM32_FLASH_TYPE_G0:
   case STM32_FLASH_TYPE_G4:
     optcr_reg = STM32Gx_FLASH_CR;
@@ -597,6 +639,9 @@ static int unlock_flash_option(stlink_t *sl) {
   case STM32_FLASH_TYPE_L4_L4P:
     optkey_reg = STM32L4_FLASH_OPTKEYR;
     break;
+  case STM32_FLASH_TYPE_L5_U5:
+    optkey_reg = STM32L5_FLASH_OPTKEYR;
+    break;
   case STM32_FLASH_TYPE_G0:
   case STM32_FLASH_TYPE_G4:
     optkey_reg = STM32Gx_FLASH_OPTKEYR;
@@ -673,6 +718,8 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) {
     cr_reg = FLASH_F7_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     cr_reg = STM32L4_FLASH_CR;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
@@ -740,7 +787,9 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) {
 static void set_flash_cr_per(stlink_t *sl, unsigned bank) {
   uint32_t cr_reg, val;
 
-  if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
+  if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
       sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) {
@@ -757,7 +806,9 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) {
 static void clear_flash_cr_per(stlink_t *sl, unsigned bank) {
   uint32_t cr_reg;
 
-  if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
+  if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
+  } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
       sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) {
@@ -798,6 +849,9 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) {
   } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
     cr_reg = STM32L4_FLASH_CR;
     cr_strt = (1 << STM32L4_FLASH_CR_STRT);
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
+    cr_strt = (1 << STM32L5_FLASH_NSCR_NSSTRT);
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
@@ -833,6 +887,10 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) {
     cr_reg = STM32L4_FLASH_CR;
     cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
     cr_pg = (1 << STM32L4_FLASH_CR_PG);
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
+    cr_mer = (1 << STM32L5_FLASH_NSCR_NSMER1) | (1 << STM32L5_FLASH_NSCR_NSMER2);
+    cr_pg = (1 << STM32L5_FLASH_NSCR_NSPG);
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
@@ -993,6 +1051,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
     val |= (1 << 0) | (1 << 1) | (1 << 2);
     stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
   } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL ||
+             sl->flash_type == STM32_FLASH_TYPE_L5_U5 ||
              sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     uint32_t val;
@@ -1010,6 +1069,24 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
       val |= ((flash_page & 0xFF) << 3);
 
       stlink_write_debug32(sl, STM32WB_FLASH_CR, val);
+    } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+      uint32_t flash_page;
+      stlink_read_debug32(sl, STM32L5_FLASH_NSCR, &val);
+      if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) {
+        flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) /
+          (uint32_t)(sl->flash_pgsz);
+        // set bank 2 for erasure
+        val |= (1 << STM32L5_FLASH_NSCR_NSBKER);
+      } else {
+        flash_page =
+            ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz));
+        // set bank 1 for erasure
+        val &= ~(1 << STM32L5_FLASH_NSCR_NSBKER);
+      }
+      // sec 6.9.9
+      val &= ~(0x7F << 3);
+      val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER);
+      stlink_write_debug32(sl, STM32L5_FLASH_NSCR, val);
     } else if (sl->flash_type == STM32_FLASH_TYPE_G0) {
       uint32_t flash_page =
           ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz));

src/flashloader.c

@@ -83,6 +83,9 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) {
     cr_reg = STM32L4_FLASH_CR;
     x &= ~STM32L4_FLASH_CR_OPBITS;
     x |= (1 << STM32L4_FLASH_CR_PG);
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) {
+    cr_reg = STM32L5_FLASH_NSCR;
+    x |= (1 << FLASH_CR_PG);
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     cr_reg = STM32Gx_FLASH_CR;
@@ -121,6 +124,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) {
     rcc = STM32G0_RCC_AHBENR;
     rcc_dma_mask = STM32G0_RCC_DMAEN;
     break;
+  case STM32_FLASH_TYPE_L5_U5:
+    rcc = STM32L5_RCC_AHB1ENR;
+    rcc_dma_mask = STM32L5_RCC_DMAEN;
+    break;
   case STM32_FLASH_TYPE_G4:
   case STM32_FLASH_TYPE_L4_L4P:
     rcc = STM32G4_RCC_AHB1ENR;
@@ -214,9 +221,10 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) {
     // set programming mode
     set_flash_cr_pg(sl, BANK_1);
   } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL ||
+             sl->flash_type == STM32_FLASH_TYPE_L5_U5 ||
              sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
-    ILOG("Starting Flash write for WB/G0/G4\n");
+    ILOG("Starting Flash write for WB/L5/G0/G4\n");
 
     unlock_flash_if(sl);         // unlock flash if necessary
     set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit
@@ -318,6 +326,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl,
       off += size;
     }
   } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL ||
+             sl->flash_type == STM32_FLASH_TYPE_L5_U5 ||
              sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
     DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz));
@@ -326,7 +335,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl,
 
       if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) {
         fprintf(stdout, "\r%3u/%3u pages written",
-                (unsigned int)(off / sl->flash_pgsz),
+                (unsigned int)(off / sl->flash_pgsz + 1),
                 (unsigned int)(len / sl->flash_pgsz));
         fflush(stdout);
       }
@@ -367,7 +376,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl,
 
       if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) {
         fprintf(stdout, "\r%3u/%3u pages written",
-                (unsigned int)(off / sl->flash_pgsz),
+                (unsigned int)(off / sl->flash_pgsz + 1),
                 (unsigned int)(len / sl->flash_pgsz));
         fflush(stdout);
       }
@@ -451,6 +460,7 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) {
       (sl->flash_type == STM32_FLASH_TYPE_F2_F4) ||
       (sl->flash_type == STM32_FLASH_TYPE_F7) ||
       (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) ||
+      (sl->flash_type == STM32_FLASH_TYPE_L5_U5) ||
       (sl->flash_type == STM32_FLASH_TYPE_WB_WL) ||
       (sl->flash_type == STM32_FLASH_TYPE_G0) ||
       (sl->flash_type == STM32_FLASH_TYPE_G4) ||

src/stlink-lib/chipid.c

@@ -105,7 +105,12 @@ void process_chipfile(char *fname) {
                 ts->flash_type = STM32_FLASH_TYPE_WB_WL;
             } else {
                 ts->flash_type = STM32_FLASH_TYPE_UNKNOWN;
-                fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n");
+                fprintf(
+                    stderr,
+                    "Failed to parse flash type or unrecognized flash type %s from file %s\n",
+                    value,
+                    fname
+                );
             }
         } else if (strcmp(word, "flash_size_reg") == 0) {
             if (sscanf(value, "%i", &ts->flash_size_reg) < 1) {