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This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

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RISC-V Specification for CHERI Extensions

This repository contains the CHERI extension specification, adding hardware capabilities to the RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

License

This work is licensed under a Creative Commons Attribution 4.0 International License (CC-BY-4.0). For details, see the LICENSE file.

Contributors

The list of contributors to this specification is maintained in the contributors file.

For guidelines on how to contribute, refer to the CONTRIBUTING file.

Building the Document

Prerequisites

To build the document, you’ll need the following tools installed on your system:

  • Make

  • asciiDoctor-pdf, asciidoctor-bibtex, asciidoctor-diagram and asciidoctor-mathematical

  • Docker

  • Python3

Cloning the Repository

git clone --recurse-submodules https://github.com/riscv/riscv-cheri.git

Building the Documentation

To start the build process, run cd ./riscv-cheri && make all.

The Makefile script will check the availability of Docker on your system:

  • If Docker is available, the documentation will be built inside a Docker container using the image riscvintl/riscv-docs-base-container-image:latest. This ensures a consistent build environment across different systems.

  • If Docker is not available, the documentation will be built directly on your system using the installed tools.

The documentation is generated from the AsciiDoctor source files in your project. The primary source file is specified by the HEADER_SOURCE variable in the Makefile.

The build process utilizes several options, including theming and font settings, and generates a PDF document as output.

Cleaning up

To clean up the generated files, run make clean. This will remove the generated PDF file.

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This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

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  • Python 75.2%
  • Makefile 17.9%
  • TeX 6.9%