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[LLDP] No LLDP table output #1605

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stcheng opened this issue Apr 16, 2018 · 1 comment
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[LLDP] No LLDP table output #1605

stcheng opened this issue Apr 16, 2018 · 1 comment
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@pavel-shirshov
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@stcheng
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stcheng commented Apr 16, 2018

Description
After the switch starts, with the command lldpshow or lldpctl there is no output of the neighbor information. Using supervisorctl restart lldpd, this issue could be manually resolved. It is possible that this is an lldpd issue.

Steps to reproduce the issue:
Currently unknown.

Version
It is seen on various recent versions.
@pavel-shirshov
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Fixed
83f81c9#diff-833cde5fbd99d17f29e8cfbd25b9d3bc

lguohan pushed a commit that referenced this issue Apr 8, 2021
@stepanblyschak
[sonic-swss] update sonic-swss submodule (#7263)
4351db7 
5c63670 (HEAD, origin/master, origin/HEAD) [intfmgrd] reach reconciled state at start when there are no interfaces configuration to process (#1695)
66e1aab [Dynamic Buffer Calc] Enhancement: coding style and LGTM alerts (#1693)
637e8d0 Skip Macsec test case till macsec orch code is made SAIv1.8.0 compatible (#1688)
872b5cb [ci]: archive swss pytests (#1690)
73cbd91 [Makefile] Reorder libsaimetadata and libswsscommon (#1689)
cba6576 Correct the sflow default sample rate (#1623)
aac71e6 Don't update pools when ingress_lossless_pool is created but the initialization hasn't finished yet (#1685)
ae5f051 Fix dynamic buffer bug occuring in rare condition (#1678)
691bd30 [voq/systemlag] Voq system lag functionality (#1605)

Signed-off-by: Stepan Blyschak <[email protected]>
raphaelt-nvidia pushed a commit to raphaelt-nvidia/sonic-buildimage that referenced this issue May 23, 2021
@stepanblyschak @raphaelt-nvidia
[sonic-swss] update sonic-swss submodule (sonic-net#7263)
f274f3f 
5c63670 (HEAD, origin/master, origin/HEAD) [intfmgrd] reach reconciled state at start when there are no interfaces configuration to process (sonic-net#1695)
66e1aab [Dynamic Buffer Calc] Enhancement: coding style and LGTM alerts (sonic-net#1693)
637e8d0 Skip Macsec test case till macsec orch code is made SAIv1.8.0 compatible (sonic-net#1688)
872b5cb [ci]: archive swss pytests (sonic-net#1690)
73cbd91 [Makefile] Reorder libsaimetadata and libswsscommon (sonic-net#1689)
cba6576 Correct the sflow default sample rate (sonic-net#1623)
aac71e6 Don't update pools when ingress_lossless_pool is created but the initialization hasn't finished yet (sonic-net#1685)
ae5f051 Fix dynamic buffer bug occuring in rare condition (sonic-net#1678)
691bd30 [voq/systemlag] Voq system lag functionality (sonic-net#1605)

Signed-off-by: Stepan Blyschak <[email protected]>
carl-nokia pushed a commit to carl-nokia/sonic-buildimage that referenced this issue Aug 7, 2021
@stepanblyschak
[sonic-swss] update sonic-swss submodule (sonic-net#7263)
16f00b9 
5c63670 (HEAD, origin/master, origin/HEAD) [intfmgrd] reach reconciled state at start when there are no interfaces configuration to process (sonic-net#1695)
66e1aab [Dynamic Buffer Calc] Enhancement: coding style and LGTM alerts (sonic-net#1693)
637e8d0 Skip Macsec test case till macsec orch code is made SAIv1.8.0 compatible (sonic-net#1688)
872b5cb [ci]: archive swss pytests (sonic-net#1690)
73cbd91 [Makefile] Reorder libsaimetadata and libswsscommon (sonic-net#1689)
cba6576 Correct the sflow default sample rate (sonic-net#1623)
aac71e6 Don't update pools when ingress_lossless_pool is created but the initialization hasn't finished yet (sonic-net#1685)
ae5f051 Fix dynamic buffer bug occuring in rare condition (sonic-net#1678)
691bd30 [voq/systemlag] Voq system lag functionality (sonic-net#1605)

Signed-off-by: Stepan Blyschak <[email protected]>
theasianpianist pushed a commit to theasianpianist/sonic-buildimage that referenced this issue Feb 5, 2022
@vganesan-nokia
[voq/systemlag] Voq system lag functionality (sonic-net#1605)
691bd30 
* [voq/systemlag] VOQ System lag functionality

Signed-off-by: vedganes <[email protected]>

Changes for voq system lag implementation
(1) Portsorch changes for allocating unique lag id from chassis ap pdb
and sending the id in system port aggregator id attribute while creating
lag local LAG
(2) Portsorch changes to synd local LAG and local LAG members to
chassis app db. The sync-ing includes the allocated unique system lag id
(3) Portsorch changes to process remote system lag from chassis app db
and create lag entry in local asic db with received system lag id
(4) Interface orch changes to identify local or remote interfaces
(for both port and lag)
(5) Orchdaemon changes in orchagent intialization to get hostname and
asic_name attributes from DEVICE_METATDATA. These are used for unique
system lag name derivation

* [vog/systemlag] VS test for system lag
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