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[Arista]: Add QoS configurations for Quicksilver (#19161)
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These are likely not the optimal configurations but a first draft.
Most of QuicksilverP and QuicksilverDD HwSku should be supported.

Co-authored-by: Samuel Angebault <[email protected]>
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@rick-arista @Staphylo
rick-arista and Staphylo authored Jun 8, 2024
1 parent c617e81 commit cd578ac
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{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}
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{%- include 'qos_config.j2' %}
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{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}
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{%- include 'qos_config.j2' %}
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0, 512, 4) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
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{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}
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{%- include 'qos_config.j2' %}
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0, 512, 2) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
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{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}
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{%- include 'qos_config.j2' %}
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0, 512, 8) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
2 changes: 2 additions & 0 deletions device/arista/x86_64-arista_7060x6_64pe/Arista-7060X6-64PE-64x400G/buffers.json.j2
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{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}
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{%- include 'qos_config.j2' %}
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6 changes: 6 additions & 0 deletions device/arista/x86_64-arista_7060x6_64pe/Arista-7060X6-64PE/buffer_ports.j2
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0, 512, 8) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
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{%- set default_topo = 't1' %}
{%- include 'buffers_config.j2' %}
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{%- include 'qos_config.j2' %}
36 changes: 36 additions & 0 deletions device/common/profiles/th5/gen/BALANCED/buffers_defaults_t0.j2
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{%- set default_cable = '5m' %}

{%- include 'buffer_ports.j2' %}

{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"type": "ingress",
"mode": "dynamic",
"size": "60000000",
"xoff": "22600000"
},
"egress_lossless_pool": {
"type": "egress",
"mode": "static",
"size": "82600000"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool": "ingress_lossless_pool",
"size": "0",
"dynamic_th": "3"
},
"egress_lossless_profile": {
"pool": "egress_lossless_pool",
"size": "0",
"static_th": "82600000"
},
"egress_lossy_profile": {
"pool": "egress_lossless_pool",
"size": "0",
"dynamic_th": "3"
}
},
{%- endmacro %}
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{%- set default_cable = '5m' %}

{%- include 'buffer_ports.j2' %}

{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"type": "ingress",
"mode": "dynamic",
"size": "60000000",
"xoff": "22600000"
},
"egress_lossless_pool": {
"type": "egress",
"mode": "static",
"size": "82600000"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool": "ingress_lossless_pool",
"size": "0",
"dynamic_th": "3"
},
"egress_lossless_profile": {
"pool": "egress_lossless_pool",
"size": "0",
"static_th": "82600000"
},
"egress_lossy_profile": {
"pool": "egress_lossless_pool",
"size": "0",
"dynamic_th": "3"
}
},
{%- endmacro %}
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# PG lossless profiles.
# speed cable size xon xoff threshold xon_offset
10000 5m 1248 2288 35776 0 2288
25000 5m 1248 2288 53248 0 2288
40000 5m 1248 2288 66560 0 2288
50000 5m 1248 2288 90272 0 2288
100000 5m 1248 2288 165568 0 2288
400000 5m 1248 2288 165568 0 2288
10000 40m 1248 2288 37024 0 2288
25000 40m 1248 2288 53248 0 2288
40000 40m 1248 2288 71552 0 2288
50000 40m 1248 2288 96096 0 2288
100000 40m 1248 2288 177632 0 2288
400000 40m 1248 2288 177632 0 2288
10000 300m 1248 2288 46176 0 2288
25000 300m 1248 2288 79040 0 2288
40000 300m 1248 2288 108160 0 2288
50000 300m 1248 2288 141856 0 2288
100000 300m 1248 2288 268736 0 2288
400000 300m 1248 2288 268736 0 2288

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