Sayma_v2_integration_support

Oxford University is providing support for Sayma v2. Here's what they've agreed to do.

C.2 Objectives

In support of Sayma v2 PCB development, a) design and characterize a low phase noise clock distribution system, and b) investigate synchronizing multiple DAC channels. Participate in review of the overall system design as relates to clocking and synchronization.

C.3 Requirements

C.3.1 Clock Distribution

Support development of a clock distribution system that enables DAC performance with the following properties.

• Phase noise at 400 MHz is
  • 10 Hz offset, < -94 decibels relative to the carrier (dBc)
  • 100 Hz offset, < -103 dBc
  • 1000 Hz offset, < -120 dBc
  • 10,000 Hz offset, < -126 dBc
• Less than -60 dBc spurious-free dynamic range (SFDR) across operating range, max amplitude.
• Less than -80 dBc cross talk at 400 MHz.

As it is a critical design parameter, Oxford will consider phase stability between DACs on separate Sayma PCBs at all stages of the design. RF phase alignment variation will be evaluated under the following test conditions:

• RF output on all channels of two Sayma PCBs, 400 MHz continuous radio frequency (RF)
• Laboratory temperature stability +/- 0.5 Celsius (C)
• Test duration 24 hours The target RF phase variation is less than 0.5 deg at 400 MHz.

C.3.2 Tasks

C.3.2.1 Support DAC-FPGA synchronization with Sayma PCB v2.0.

C.3.2.2 Participate in high-level design review.

C.3.2.3 Participate in detailed design review

C.3.2.4 Evaluate phase alignment and synchronization between multiple output channels of multiple Sayma PCBs.

C.3.2.5 Measure DAC phase stability.

C.3.2.6 Support development a clock distribution infrastructure similar to White Rabbit (WR) Digital Dual Mixer Time Difference (DDMTD). This includes support of related integrated circuit (IC) components including the Si549 IC.

C.3.2.7 Write and validate driver for the ADF4356 IC. And shall troubleshoot the existing driver for the HMC830 PLL IC.