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Add Sifive Xsfvqmacc extension intrinsics #5

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Add Sifive Xsfvqmacc extension intrinsics #5

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f053bad
RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.
yulong18 Nov 22, 2024
1f32394
RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.
yulong18 Nov 21, 2024
e837693
RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.
yulong18 Nov 22, 2024
124e727
RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions.
yulong18 Nov 22, 2024
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2 changes: 1 addition & 1 deletion gcc/config.gcc
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Original file line number Diff line number Diff line change
Expand Up @@ -557,7 +557,7 @@ riscv*)
cpu_type=riscv
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o"
extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o riscv-avlprop.o"
extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o sifive-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h riscv_cmo.h"
Expand Down
2 changes: 1 addition & 1 deletion gcc/config/riscv/generic-vector-ooo.md
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Expand Up @@ -69,7 +69,7 @@

;; Vector float multiplication and FMA.
(define_insn_reservation "vec_fmul" 6
(eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16")
(eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16,sf_vqmacc,sf_vfnrclip")
"vxu_ooo_issue,vxu_ooo_alu")

;; Vector crypto, assumed to be a generic operation for now.
Expand Down
57 changes: 57 additions & 0 deletions gcc/config/riscv/genrvv-type-indexer.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -250,11 +250,18 @@ main (int argc, const char **argv)
fprintf (fp, " /*MASK*/ %s,\n", mode.str ().c_str ());
fprintf (fp, " /*SIGNED*/ INVALID,\n");
fprintf (fp, " /*UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*SIGNED_EEW8_INDEX*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INDEX*/ INVALID,\n", eew);
fprintf (fp, " /*SHIFT*/ INVALID,\n");
fprintf (fp, " /*DOUBLE_TRUNC*/ INVALID,\n");
fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*OCT_TRUNC*/ INVALID,\n");
fprintf (fp, " /*DOUBLE_TRUNC_SCALAR*/ INVALID,\n");
fprintf (fp, " /*DOUBLE_TRUNC_SIGNED*/ INVALID,\n");
Expand All @@ -266,6 +273,9 @@ main (int argc, const char **argv)
fprintf (fp, " /*FLOAT*/ INVALID,\n");
fprintf (fp, " /*LMUL1*/ INVALID,\n");
fprintf (fp, " /*WLMUL1*/ INVALID,\n");
fprintf (fp, " /*QLMUL1*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_UNSIGNED*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);

Expand Down Expand Up @@ -307,6 +317,10 @@ main (int argc, const char **argv)
inttype (sew, lmul_log2, /*unsigned_p*/ false).c_str ());
fprintf (fp, " /*UNSIGNED*/ %s,\n",
inttype (sew, lmul_log2, /*unsigned_p*/ true).c_str ());
fprintf (fp, " /*SIGNED_EEW8_INDEX*/ %s,\n",
same_ratio_eew_type (sew, lmul_log2, 8,
/*unsigned_p*/ false, false)
.c_str ());
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INDEX*/ %s,\n", eew,
same_ratio_eew_type (sew, lmul_log2, eew,
Expand All @@ -322,6 +336,18 @@ main (int argc, const char **argv)
same_ratio_eew_type (sew, lmul_log2, sew / 4, unsigned_p,
false)
.c_str ());
fprintf (fp, " /*QUAD_EMUL*/ %s,\n",
inttype (8, lmul_log2 - 1, unsigned_p).c_str ());
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ %s,\n",
inttype (8, lmul_log2 - 1, false).c_str ());
fprintf (fp, " /*QUAD_EMUL_UNSIGNED*/ %s,\n",
inttype (8, lmul_log2 - 1, true).c_str ());
fprintf (fp, " /*QUAD_FIX*/ %s,\n",
inttype (8, lmul_log2, unsigned_p).c_str ());
fprintf (fp, " /*QUAD_FIX_SIGNED*/ %s,\n",
inttype (8, lmul_log2, false).c_str ());
fprintf (fp, " /*QUAD_FIX_UNSIGNED*/ %s,\n",
inttype (8, lmul_log2, true).c_str ());
fprintf (fp, " /*OCT_TRUNC*/ %s,\n",
same_ratio_eew_type (sew, lmul_log2, sew / 8, unsigned_p,
false)
Expand Down Expand Up @@ -352,6 +378,12 @@ main (int argc, const char **argv)
inttype (sew, /*lmul_log2*/ 0, unsigned_p).c_str ());
fprintf (fp, " /*WLMUL1*/ %s,\n",
inttype (sew * 2, /*lmul_log2*/ 0, unsigned_p).c_str ());
fprintf (fp, " /*QLMUL1*/ %s,\n",
inttype (8, /*lmul_log2*/ 0, unsigned_p).c_str ());
fprintf (fp, " /*QLMUL1_SIGNED*/ %s,\n",
inttype (8, /*lmul_log2*/ 0, false).c_str ());
fprintf (fp, " /*QLMUL1_UNSIGNED*/ %s,\n",
inttype (8, /*lmul_log2*/ 0, true).c_str ());
for (unsigned eew : {8, 16, 32, 64})
{
if (eew == sew)
Expand Down Expand Up @@ -405,6 +437,7 @@ main (int argc, const char **argv)
inttype (16, lmul_log2, /*unsigned_p*/ false).c_str ());
fprintf (fp, " /*UNSIGNED*/ %s,\n",
inttype (16, lmul_log2, /*unsigned_p*/ true).c_str ());
fprintf (fp, " /*SIGNED_EEW8_INDEX*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (
fp, " /*EEW%d_INDEX*/ %s,\n", eew,
Expand All @@ -413,6 +446,12 @@ main (int argc, const char **argv)
fprintf (fp, " /*DOUBLE_TRUNC*/ %s,\n",
same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ());
fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*OCT_TRUNC*/ INVALID,\n");
fprintf (fp, " /*DOUBLE_TRUNC_SCALAR*/ %s,\n",
same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ());
Expand All @@ -430,6 +469,10 @@ main (int argc, const char **argv)
bfloat16_type (/*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*WLMUL1*/ %s,\n",
bfloat16_wide_type (/*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*QLMUL1*/ %s,\n",
bfloat16_wide_type (/*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_UNSIGNED*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);

Expand Down Expand Up @@ -468,6 +511,10 @@ main (int argc, const char **argv)
inttype (sew, lmul_log2, /*unsigned_p*/ false).c_str ());
fprintf (fp, " /*UNSIGNED*/ %s,\n",
inttype (sew, lmul_log2, /*unsigned_p*/ true).c_str ());
fprintf (fp, " /*SIGNED_EEW8_INDEX*/ %s,\n",
same_ratio_eew_type (sew, lmul_log2, 8,
/*unsigned_p*/ false, false)
.c_str ());
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INDEX*/ %s,\n", eew,
same_ratio_eew_type (sew, lmul_log2, eew,
Expand All @@ -478,6 +525,12 @@ main (int argc, const char **argv)
same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true)
.c_str ());
fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_FIX_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*OCT_TRUNC*/ INVALID,\n");
fprintf (fp, " /*DOUBLE_TRUNC_SCALAR*/ %s,\n",
same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true)
Expand All @@ -501,6 +554,10 @@ main (int argc, const char **argv)
floattype (sew, /*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*WLMUL1*/ %s,\n",
floattype (sew * 2, /*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*QLMUL1*/ %s,\n",
floattype (sew / 4, /*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_UNSIGNED*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);

Expand Down
6 changes: 0 additions & 6 deletions gcc/config/riscv/riscv-vector-builtins-bases.cc
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Expand Up @@ -58,12 +58,6 @@ enum lst_type
LST_INDEXED,
};

enum frm_op_type
{
NO_FRM,
HAS_FRM,
};

/* Helper function to fold vleff and vlsegff. */
static gimple *
fold_fault_load (gimple_folder &f)
Expand Down
6 changes: 6 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-bases.h
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Expand Up @@ -23,6 +23,12 @@

namespace riscv_vector {

enum frm_op_type
{
NO_FRM,
HAS_FRM,
};

namespace bases {
extern const function_base *const vsetvl;
extern const function_base *const vsetvlmax;
Expand Down
58 changes: 58 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-shapes.cc
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Expand Up @@ -1287,6 +1287,62 @@ struct crypto_vv_no_op_type_def : public build_base
}
};

/* sf_vqmacc_def class. */
struct sf_vqmacc_def : public build_base
{
char *get_name (function_builder &b, const function_instance &instance,
bool overloaded_p) const override
{
b.append_base_name (instance.base_name);

/* vop --> vop_v. */
b.append_name (operand_suffixes[instance.op_info->op]);

/* Return nullptr if it can not be overloaded. */
if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
return b.finish_name ();

if (!overloaded_p)
{
/* vop_v --> vop_v_<type>. */
b.append_name (type_suffixes[instance.type.index].vector);
}

/* According to SIFIVE vector-intrinsic-doc, it adds "_tu" suffix
for vop_m C++ overloaded API.*/
b.append_name (predication_suffixes[instance.pred]);

return b.finish_name ();
}
};

/* sf_vfnrclip_def class. Handle instructions like vfnrclip. */
struct sf_vfnrclip_def : public build_base
{
char *get_name (function_builder &b, const function_instance &instance,
bool overloaded_p) const override
{
b.append_base_name (instance.base_name);

/* Return nullptr if it can not be overloaded. */
if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
return b.finish_name ();

if (!overloaded_p)
{
vector_type_index ret_type_idx
= instance.op_info->ret.get_function_type_index (instance.type.index);
/* v --> v_<type>. */
b.append_name (type_suffixes[ret_type_idx].vector);
}

/* According to SIFIVE vector-intrinsic-doc, it adds "_m\_tu\
_tum\_tumu\_mu" suffixes for vop_m C++ overloaded API.*/
b.append_name (predication_suffixes[instance.pred]);
return b.finish_name ();
}
};

SHAPE(vsetvl, vsetvl)
SHAPE(vsetvl, vsetvlmax)
SHAPE(loadstore, loadstore)
Expand Down Expand Up @@ -1321,4 +1377,6 @@ SHAPE(seg_fault_load, seg_fault_load)
SHAPE(crypto_vv, crypto_vv)
SHAPE(crypto_vi, crypto_vi)
SHAPE(crypto_vv_no_op_type, crypto_vv_no_op_type)
SHAPE (sf_vqmacc, sf_vqmacc)
SHAPE (sf_vfnrclip, sf_vfnrclip)
} // end namespace riscv_vector
3 changes: 3 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-shapes.h
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Expand Up @@ -59,6 +59,9 @@ extern const function_shape *const seg_fault_load;
extern const function_shape *const crypto_vv;
extern const function_shape *const crypto_vi;
extern const function_shape *const crypto_vv_no_op_type;
/* Sifive vendor extension. */
extern const function_shape *const sf_vqmacc;
extern const function_shape *const sf_vfnrclip;
}

} // end namespace riscv_vector
Expand Down
12 changes: 12 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-types.def
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Expand Up @@ -357,6 +357,12 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_CRYPTO_SEW64_OPS(TYPE, REQUIRE)
#endif

/* Use "DEF_RVV_QMACC_OPS" macro include signed integer which will
be iterated and registered as intrinsic functions. */
#ifndef DEF_RVV_QMACC_OPS
#define DEF_RVV_QMACC_OPS(TYPE, REQUIRE)
#endif

DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_I_OPS (vint8mf4_t, 0)
DEF_RVV_I_OPS (vint8mf2_t, 0)
Expand Down Expand Up @@ -1440,6 +1446,11 @@ DEF_RVV_CRYPTO_SEW64_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_CRYPTO_SEW64_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_CRYPTO_SEW64_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)

DEF_RVV_QMACC_OPS (vint32m1_t, 0)
DEF_RVV_QMACC_OPS (vint32m2_t, 0)
DEF_RVV_QMACC_OPS (vint32m4_t, 0)
DEF_RVV_QMACC_OPS (vint32m8_t, 0)

#undef DEF_RVV_I_OPS
#undef DEF_RVV_U_OPS
#undef DEF_RVV_F_OPS
Expand Down Expand Up @@ -1494,3 +1505,4 @@ DEF_RVV_CRYPTO_SEW64_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
#undef DEF_RVV_CRYPTO_SEW32_OPS
#undef DEF_RVV_CRYPTO_SEW64_OPS
#undef DEF_RVV_F32_OPS
#undef DEF_RVV_QMACC_OPS
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