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Committing changes checked into Koala missing on Master #518

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Jul 28, 2020
Merged

Committing changes checked into Koala missing on Master #518

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5e7e8bc
Update to pickup all Koala missing commits
bsousi5 Jul 28, 2020
5c19fc5
Update BSP files
bsousi5 Jul 28, 2020
0e8d167
Update HCA example to macth scl-metal
bsousi5 Jul 28, 2020
b90a3ea
Revert "Update HCA example to macth scl-metal"
bsousi5 Jul 28, 2020
492f616
Revert SCL metal and HCA example
bsousi5 Jul 28, 2020
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2 changes: 1 addition & 1 deletion FreeRTOS-metal
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Submodule FreeRTOS-metal updated 2 files
+2 −6 .github/workflows/release.yml
+12 −1 templates/Bridge_Freedom-metal_FreeRTOS.h.in
2 changes: 1 addition & 1 deletion Segger_SystemView-metal
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Submodule Segger_SystemView-metal updated 1 files
+2 −6 .github/workflows/release.yml
2 changes: 1 addition & 1 deletion bsp/freedom-e310-arty/metal.default.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -260,7 +260,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
2 changes: 1 addition & 1 deletion bsp/freedom-e310-arty/metal.freertos.lds
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Expand Up @@ -281,7 +281,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
2 changes: 1 addition & 1 deletion bsp/freedom-e310-arty/metal.ramrodata.lds
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Expand Up @@ -264,7 +264,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
11 changes: 1 addition & 10 deletions bsp/freedom-e310-arty/metal.scratchpad.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -72,15 +72,6 @@ SECTIONS
* certain core features */
PROVIDE(__metal_chicken_bit = 1);

/* The memory_ecc_scrub bit is used by _entry code to enable/disable
* memories scrubbing to zero */
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 );
PROVIDE( metal_itim_0_memory_start = 0x8000000 );
PROVIDE( metal_itim_0_memory_end = 0x8000000 + 0x4000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -261,7 +252,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
6 changes: 4 additions & 2 deletions bsp/qemu-sifive-e31/metal.default.lds
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Expand Up @@ -75,8 +75,10 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -257,7 +259,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
6 changes: 4 additions & 2 deletions bsp/qemu-sifive-e31/metal.freertos.lds
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Expand Up @@ -78,8 +78,10 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -278,7 +280,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
6 changes: 4 additions & 2 deletions bsp/qemu-sifive-e31/metal.ramrodata.lds
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Expand Up @@ -79,8 +79,10 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -261,7 +263,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
9 changes: 1 addition & 8 deletions bsp/qemu-sifive-e31/metal.scratchpad.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -71,13 +71,6 @@ SECTIONS
* certain core features */
PROVIDE(__metal_chicken_bit = 1);

/* The memory_ecc_scrub bit is used by _entry code to enable/disable
* memories scrubbing to zero */
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -258,7 +251,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
6 changes: 4 additions & 2 deletions bsp/qemu-sifive-s51/metal.default.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -75,8 +75,10 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -257,7 +259,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
6 changes: 4 additions & 2 deletions bsp/qemu-sifive-s51/metal.freertos.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -78,8 +78,10 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -278,7 +280,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
6 changes: 4 additions & 2 deletions bsp/qemu-sifive-s51/metal.ramrodata.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,10 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -261,7 +263,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
9 changes: 1 addition & 8 deletions bsp/qemu-sifive-s51/metal.scratchpad.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -71,13 +71,6 @@ SECTIONS
* certain core features */
PROVIDE(__metal_chicken_bit = 1);

/* The memory_ecc_scrub bit is used by _entry code to enable/disable
* memories scrubbing to zero */
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -258,7 +251,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
4 changes: 2 additions & 2 deletions bsp/qemu-sifive-u54/metal.default.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
Expand Down Expand Up @@ -258,7 +258,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
4 changes: 2 additions & 2 deletions bsp/qemu-sifive-u54/metal.freertos.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
Expand Down Expand Up @@ -279,7 +279,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
4 changes: 2 additions & 2 deletions bsp/qemu-sifive-u54/metal.ramrodata.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
Expand Down Expand Up @@ -262,7 +262,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
11 changes: 1 addition & 10 deletions bsp/qemu-sifive-u54/metal.scratchpad.lds
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -70,15 +70,6 @@ SECTIONS
* certain core features */
PROVIDE(__metal_chicken_bit = 1);

/* The memory_ecc_scrub bit is used by _entry code to enable/disable
* memories scrubbing to zero */
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -259,7 +250,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
4 changes: 2 additions & 2 deletions bsp/qemu-sifive-u54mc/metal.default.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
Expand Down Expand Up @@ -261,7 +261,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
4 changes: 2 additions & 2 deletions bsp/qemu-sifive-u54mc/metal.freertos.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
Expand Down Expand Up @@ -282,7 +282,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
4 changes: 2 additions & 2 deletions bsp/qemu-sifive-u54mc/metal.ramrodata.lds
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
Expand Down Expand Up @@ -265,7 +265,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
11 changes: 1 addition & 10 deletions bsp/qemu-sifive-u54mc/metal.scratchpad.lds
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -70,15 +70,6 @@ SECTIONS
* certain core features */
PROVIDE(__metal_chicken_bit = 1);

/* The memory_ecc_scrub bit is used by _entry code to enable/disable
* memories scrubbing to zero */
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_memory_0_memory_start = 0x80000000 );
PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -262,7 +253,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >testram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
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