Implicit register binding for hlsl to non-hlsl targets

source/slang/slang-parameter-binding.cpp

@@ -1146,12 +1146,12 @@ static void addExplicitParameterBindings_GLSL(
     // See if we can infer vulkan binding from HLSL if we have such options set, we know 
     // we can't map
     auto hlslToVulkanLayoutOptions = context->getTargetProgram()->getHLSLToVulkanLayoutOptions();
-
+    bool warnedMissingVulkanLayoutModifier = false;
     // If we have the options, but cannot infer bindings, we don't need to go further
     if (hlslToVulkanLayoutOptions == nullptr || !hlslToVulkanLayoutOptions->canInferBindings())
     {
+        warnedMissingVulkanLayoutModifier = true;
         _maybeDiagnoseMissingVulkanLayoutModifier(context, varDecl.as<VarDeclBase>());
-        return;
     }
 
     // We need an HLSL register semantic to to infer from
@@ -1190,20 +1190,31 @@ static void addExplicitParameterBindings_GLSL(
     // If inference is not enabled for this kind, we can issue a warning
     if (!hlslToVulkanLayoutOptions->canInfer(vulkanKind, hlslInfo.space))
     {
-        _maybeDiagnoseMissingVulkanLayoutModifier(context, varDecl.as<VarDeclBase>());
-        return;
+        if(!warnedMissingVulkanLayoutModifier)
+            _maybeDiagnoseMissingVulkanLayoutModifier(context, varDecl.as<VarDeclBase>());
     }
 
     // We use the HLSL binding directly (even though this notionally for GLSL/Vulkan)
     // We'll do the shifting at later later point in _maybeApplyHLSLToVulkanShifts
+    //resInfo = typeLayout->findOrAddResourceInfo(hlslInfo.kind);
     resInfo = typeLayout->findOrAddResourceInfo(hlslInfo.kind);
-    
+
     semanticInfo.kind = resInfo->kind;
     semanticInfo.index = UInt(hlslInfo.index);
     semanticInfo.space = UInt(hlslInfo.space);
-
+
+    if (resInfo->count.isFinite() && resInfo->count.getFiniteValue() == 0)
+    {
+        // hlsl objects are not going to set on a descriptor table slot
+        if (auto descriptorTableSlot = typeLayout->findOrAddResourceInfo(LayoutResourceKind::DescriptorTableSlot))
+        {
+            descriptorTableSlot->count = 0;
+        }
+        resInfo->count = 1;
+    }
     const LayoutSize count = resInfo->count;
 
+
     addExplicitParameterBinding(context, parameterInfo, as<VarDeclBase>(varDecl.getDecl()), semanticInfo, count);
 }
 

tests/hlsl/register-syntax.slang

@@ -0,0 +1,48 @@
+//TEST:SIMPLE(filecheck=CHECK_GLSL): -target glsl -stage compute -entry computeMain
+//TEST:SIMPLE(filecheck=CHECK_HLSL): -target hlsl -stage compute -entry computeMain
+//CHECK_HLSL: u4, space2
+//CHECK_HLSL: u5, space1
+//CHECK_HLSL: u6
+//CHECK_HLSL: u7
+//CHECK_HLSL: u9
+//CHECK_HLSL: u12
+
+//CHECK_GLSL: binding = 4, set = 2
+//CHECK_GLSL: binding = 5, set = 1
+//CHECK_GLSL: binding = 6
+//CHECK_GLSL: binding = 7
+//CHECK_GLSL: binding = 10
+//CHECK_GLSL: binding = 12
+
+[[vk::binding(4,2)]]
+RWStructuredBuffer<int> b0 : register(u4, space2);
+
+RWStructuredBuffer<int> b1 : register(u5, space1);
+
+RWStructuredBuffer<int> b2 : register(u6);
+
+[[vk::binding(7,0)]]
+RWStructuredBuffer<int> b3 : register(u7, space0);
+
+[[vk::binding(10,0)]]
+RWStructuredBuffer<int> b4[2] : register(u9);
+
+RWStructuredBuffer<int> b5[2] : register(u12);
+
+[numthreads(1, 1, 1)]
+void computeMain(int3 dispatchThreadID : SV_DispatchThreadID)
+{
+	int tid = dispatchThreadID.x;
+	b0[0] = 1;
+
+    b1[0] = 1;
+
+    b2[0] = 1;
+
+    b3[0] = 1;
+
+    b4[0][0] = 1;
+    b4[0][1] = 1;
+
+    b5[0][1] = 1;
+}